From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 14 Oct 2016 15:49:04 +0000 (+0200)
Subject: boards/targets/sim: fix
X-Git-Tag: 24jan2021_ls180~1930
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7a9cf57cfe5555c3bb2f54d2907465d7b0537c1e;p=litex.git

boards/targets/sim: fix
---

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 9c892911..0f0d657d 100755
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -51,7 +51,7 @@ class BaseSoC(SoCSDRAM):
             self.register_sdram(self.sdrphy,
                                 sdram_module.geom_settings,
                                 sdram_module.timing_settings,
-                                ControllerSettings(with_refresh=False))
+                                controller_settings=ControllerSettings(with_refresh=False))
             # reduce memtest size to speed up simulation
             self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
             self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)