From: Andrew Waterman <andrew@sifive.com>
Date: Fri, 4 Aug 2017 07:23:04 +0000 (-0700)
Subject: Improve RVC test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ab7ad44e66ba9bc2d91e04773efa4f87a1d8a3b;p=riscv-tests.git

Improve RVC test

Make the page-crossing instruction non-idempotent to detect erroneously
executing the first 16 bits of the instruction with garbage MSBs.
---

diff --git a/benchmarks/common/test.ld b/benchmarks/common/test.ld
index ada0862..4f8892e 100644
--- a/benchmarks/common/test.ld
+++ b/benchmarks/common/test.ld
@@ -25,7 +25,8 @@ SECTIONS
   . = 0x80000000;
   .text.init : { *(.text.init) }
 
-  .tohost ALIGN(0x1000) : { *(.tohost) }
+  . = ALIGN(0x1000);
+  .tohost : { *(.tohost) }
 
   .text : { *(.text) }
 
diff --git a/env b/env
index d7b2fdc..db0bfa2 160000
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit d7b2fdc9ed30163ac7e4f5cfc502710e862a112e
+Subproject commit db0bfa223142e56b17dae6d92610f195014bbb80
diff --git a/isa/rv64uc/rvc.S b/isa/rv64uc/rvc.S
index 2b8acd2..b0766a9 100644
--- a/isa/rv64uc/rvc.S
+++ b/isa/rv64uc/rvc.S
@@ -22,8 +22,7 @@ RVTEST_CODE_BEGIN
   // Make sure fetching a 4-byte instruction across a page boundary works.
   li TESTNUM, 2
   li a1, 666
-  li a2, 1
-  RVC_TEST_CASE (2, a1, 2, \
+  TEST_CASE (2, a1, 667, \
         j 1f; \
         .align 3; \
         data: \
@@ -31,7 +30,7 @@ RVTEST_CODE_BEGIN
           .dword 0xfedcba9876543210; \
         .align 12; \
         .skip 4094; \
-      1: addi a1, a2, 1)
+      1: addi a1, a1, 1)
 
   li sp, 0x1234
   RVC_TEST_CASE (3, a0, 0x1234 + 1020, c.addi4spn a0, sp, 1020)