From: Jordi Vaquero <jordi.vaquero@metempsy.com>
Date: Mon, 13 Jan 2020 09:47:55 +0000 (+0100)
Subject: arch-arm: Fix EL2 target exception level for SP alignment fault.
X-Git-Tag: v19.0.0.0~94
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ac4607385f8490b2a12acaef73f2f31583160f0;p=gem5.git

arch-arm: Fix EL2 target exception level for SP alignment fault.

This commit fixes the target exception Level EL2 for alignmemt fault, it
is based on HCR_EL2.tge bit.

Change-Id: Ief78b2aa0c86f1c3d9a5d3ca00121d163a9d6a86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24303
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 5a7b8e8ea..bd38fdccb 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -1541,6 +1541,14 @@ PCAlignmentFault::routeToHyp(ThreadContext *tc) const
 SPAlignmentFault::SPAlignmentFault()
 {}
 
+bool
+SPAlignmentFault::routeToHyp(ThreadContext *tc) const
+{
+    assert(from64);
+    HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
+    return EL2Enabled(tc) && hcr.tge==1;
+}
+
 SystemError::SystemError()
 {}
 
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 3f61bc722..508fd034e 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -571,6 +571,7 @@ class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault>
 {
   public:
     SPAlignmentFault();
+    bool routeToHyp(ThreadContext *tc) const override;
 };
 
 /// System error (AArch64 only)