From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 26 Jul 2014 12:38:33 +0000 (+0200)
Subject: Added RTLIL::Module::connections()
X-Git-Tag: yosys-0.4~418
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ac9dc7f6eab40b3853583848933c4a8a94df9c9;p=yosys.git

Added RTLIL::Module::connections()
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ce4ecea6f..1638682c1 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -883,6 +883,11 @@ void RTLIL::Module::connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs
 	connections_.push_back(RTLIL::SigSig(lhs, rhs));
 }
 
+const std::vector<RTLIL::SigSig> &RTLIL::Module::connections()
+{
+	return connections_;
+}
+
 void RTLIL::Module::fixup_ports()
 {
 	std::vector<RTLIL::Wire*> all_ports;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 4f91b720d..1775975d5 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -290,6 +290,7 @@ struct RTLIL::Module
 
 	void connect(const RTLIL::SigSig &conn);
 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
+	const std::vector<RTLIL::SigSig> &connections();
 	void fixup_ports();
 
 	template<typename T> void rewrite_sigspecs(T functor);