From: Xan <Xan@web>
Date: Wed, 25 Apr 2018 04:58:53 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5558
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7acaad54140d0b6cfe488015aad26c20ab23b638;p=libreriscv.git

---

diff --git a/A_Harmonised_RVV_and_Packed_SIMD.mdwn b/A_Harmonised_RVV_and_Packed_SIMD.mdwn
index b863b5f98..c4343bde5 100644
--- a/A_Harmonised_RVV_and_Packed_SIMD.mdwn
+++ b/A_Harmonised_RVV_and_Packed_SIMD.mdwn
@@ -1,6 +1,6 @@
 ## Proposal to harmonise RV Vector spec with Packed SIMD ("Harmonised" RVP)
 
-##### MVL, setvl instruction & VL CSR work as per RVV.
+##### MVL, setvl instruction & VL CSR work as per RV Vector spec.
 
 ##### VLD and VST are supported