From: Hui Zhu Date: Thu, 30 Apr 2009 03:12:17 +0000 (+0000) Subject: I386 architecture process record and replay support. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ad10968513bdf1f4af09a74f6b51547547ad2bd;p=binutils-gdb.git I386 architecture process record and replay support. * i386-tdep.c (PREFIX_REPZ, PREFIX_REPNZ, PREFIX_LOCK, PREFIX_DATA, PREFIX_ADDR): New macros. Help decode the i386 instruction set. (aflag, dflag, override, modrm, mod, reg, rm, ot, i386_record_pc): New variables. Ditto. (i386_record_modrm, i386_record_lea_modrm_addr, i386_record_lea_modrm): New functions. Ditto. (i386_process_record): New function. Parse the instruction in address "addr" and record the values of registers and memory that will be changed by this instruction. (i386_gdbarch_init): Set "i386_process_record" to GDBARCH "process_record" interface. * i386-tdep.h (gdbarch_tdep): New function pointers "i386_intx80_record" and "i386_sysenter_record" that point to the function that can record "intx80" and "sysenter" execute log. --- diff --git a/gdb/ChangeLog b/gdb/ChangeLog index ea1c14eb514..afe7560f19c 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,25 @@ +2009-04-30 Hui Zhu + Michael Snyder + + I386 architecture process record and replay support. + + * i386-tdep.c (PREFIX_REPZ, PREFIX_REPNZ, PREFIX_LOCK, + PREFIX_DATA, PREFIX_ADDR): New macros. Help decode the i386 + instruction set. + (aflag, dflag, override, modrm, mod, reg, rm, ot, + i386_record_pc): New variables. Ditto. + (i386_record_modrm, i386_record_lea_modrm_addr, + i386_record_lea_modrm): New functions. Ditto. + (i386_process_record): New function. Parse the instruction in + address "addr" and record the values of registers and memory + that will be changed by this instruction. + (i386_gdbarch_init): Set "i386_process_record" to GDBARCH + "process_record" interface. + * i386-tdep.h (gdbarch_tdep): New function pointers + "i386_intx80_record" and "i386_sysenter_record" that point to + the function that can record "intx80" and "sysenter" execute + log. + 2009-04-30 Hui Zhu Michael Snyder diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c index b74270adc64..55c4c6f561b 100644 --- a/gdb/i386-tdep.c +++ b/gdb/i386-tdep.c @@ -50,6 +50,9 @@ #include "i386-tdep.h" #include "i387-tdep.h" +#include "record.h" +#include + /* Register names. */ static char *i386_register_names[] = @@ -2671,167 +2674,2575 @@ i386_skip_permanent_breakpoint (struct regcache *regcache) } - -static struct gdbarch * -i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) -{ - struct gdbarch_tdep *tdep; - struct gdbarch *gdbarch; - - /* If there is already a candidate, use it. */ - arches = gdbarch_list_lookup_by_info (arches, &info); - if (arches != NULL) - return arches->gdbarch; - - /* Allocate space for the new architecture. */ - tdep = XCALLOC (1, struct gdbarch_tdep); - gdbarch = gdbarch_alloc (&info, tdep); - - /* General-purpose registers. */ - tdep->gregset = NULL; - tdep->gregset_reg_offset = NULL; - tdep->gregset_num_regs = I386_NUM_GREGS; - tdep->sizeof_gregset = 0; +#define PREFIX_REPZ 0x01 +#define PREFIX_REPNZ 0x02 +#define PREFIX_LOCK 0x04 +#define PREFIX_DATA 0x08 +#define PREFIX_ADDR 0x10 - /* Floating-point registers. */ - tdep->fpregset = NULL; - tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; +/* operand size */ +enum +{ + OT_BYTE = 0, + OT_WORD, + OT_LONG, +}; - /* The default settings include the FPU registers, the MMX registers - and the SSE registers. This can be overridden for a specific ABI - by adjusting the members `st0_regnum', `mm0_regnum' and - `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers - will show up in the output of "info all-registers". Ideally we - should try to autodetect whether they are available, such that we - can prevent "info all-registers" from displaying registers that - aren't available. +/* i386 arith/logic operations */ +enum +{ + OP_ADDL, + OP_ORL, + OP_ADCL, + OP_SBBL, + OP_ANDL, + OP_SUBL, + OP_XORL, + OP_CMPL, +}; - NOTE: kevinb/2003-07-13: ... if it's a choice between printing - [the SSE registers] always (even when they don't exist) or never - showing them to the user (even when they do exist), I prefer the - former over the latter. */ +struct i386_record_s +{ + struct regcache *regcache; + CORE_ADDR addr; + int aflag; + int dflag; + int override; + uint8_t modrm; + uint8_t mod, reg, rm; + int ot; +}; - tdep->st0_regnum = I386_ST0_REGNUM; +/* Parse "modrm" part in current memory address that irp->addr point to + Return -1 if something wrong. */ - /* The MMX registers are implemented as pseudo-registers. Put off - calculating the register number for %mm0 until we know the number - of raw registers. */ - tdep->mm0_regnum = 0; +static int +i386_record_modrm (struct i386_record_s *irp) +{ + if (target_read_memory (irp->addr, &irp->modrm, 1)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading memory at " + "addr 0x%s len = 1.\n"), + paddr_nz (irp->addr)); + return -1; + } + irp->addr++; + irp->mod = (irp->modrm >> 6) & 3; + irp->reg = (irp->modrm >> 3) & 7; + irp->rm = irp->modrm & 7; - /* I386_NUM_XREGS includes %mxcsr, so substract one. */ - tdep->num_xmm_regs = I386_NUM_XREGS - 1; + return 0; +} - tdep->jb_pc_offset = -1; - tdep->struct_return = pcc_struct_return; - tdep->sigtramp_start = 0; - tdep->sigtramp_end = 0; - tdep->sigtramp_p = i386_sigtramp_p; - tdep->sigcontext_addr = NULL; - tdep->sc_reg_offset = NULL; - tdep->sc_pc_offset = -1; - tdep->sc_sp_offset = -1; +/* Get the memory address that current instruction write to and set it to + the argument "addr". + Return -1 if something wrong. */ - /* The format used for `long double' on almost all i386 targets is - the i387 extended floating-point format. In fact, of all targets - in the GCC 2.95 tree, only OSF/1 does it different, and insists - on having a `long double' that's not `long' at all. */ - set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); +static int +i386_record_lea_modrm_addr (struct i386_record_s *irp, uint32_t * addr) +{ + uint8_t tmpu8; + uint16_t tmpu16; + uint32_t tmpu32; - /* Although the i387 extended floating-point has only 80 significant - bits, a `long double' actually takes up 96, probably to enforce - alignment. */ - set_gdbarch_long_double_bit (gdbarch, 96); + *addr = 0; + if (irp->aflag) + { + /* 32 bits */ + int havesib = 0; + uint8_t scale = 0; + uint8_t index = 0; + uint8_t base = irp->rm; - /* The default ABI includes general-purpose registers, - floating-point registers, and the SSE registers. */ - set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); - set_gdbarch_register_name (gdbarch, i386_register_name); - set_gdbarch_register_type (gdbarch, i386_register_type); + if (base == 4) + { + havesib = 1; + if (target_read_memory (irp->addr, &tmpu8, 1)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading memory " + "at addr 0x%s len = 1.\n"), + paddr_nz (irp->addr)); + return -1; + } + irp->addr++; + scale = (tmpu8 >> 6) & 3; + index = ((tmpu8 >> 3) & 7); + base = (tmpu8 & 7); + } - /* Register numbers of various important registers. */ - set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ - set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ - set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ - set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ + switch (irp->mod) + { + case 0: + if ((base & 7) == 5) + { + base = 0xff; + if (target_read_memory (irp->addr, (gdb_byte *) addr, 4)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading " + "memory at addr 0x%s len = 4.\n"), + paddr_nz (irp->addr)); + return -1; + } + irp->addr += 4; + } + else + { + *addr = 0; + } + break; + case 1: + if (target_read_memory (irp->addr, &tmpu8, 1)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading memory " + "at addr 0x%s len = 1.\n"), + paddr_nz (irp->addr)); + return -1; + } + irp->addr++; + *addr = (int8_t) tmpu8; + break; + case 2: + if (target_read_memory (irp->addr, (gdb_byte *) addr, 4)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading memory " + "at addr 0x%s len = 4.\n"), + paddr_nz (irp->addr)); + return -1; + } + irp->addr += 4; + break; + } - /* NOTE: kettenis/20040418: GCC does have two possible register - numbering schemes on the i386: dbx and SVR4. These schemes - differ in how they number %ebp, %esp, %eflags, and the - floating-point registers, and are implemented by the arrays - dbx_register_map[] and svr4_dbx_register_map in - gcc/config/i386.c. GCC also defines a third numbering scheme in - gcc/config/i386.c, which it designates as the "default" register - map used in 64bit mode. This last register numbering scheme is - implemented in dbx64_register_map, and is used for AMD64; see - amd64-tdep.c. + if (base != 0xff) + { + regcache_raw_read (irp->regcache, base, (gdb_byte *) & tmpu32); + *addr += tmpu32; + } - Currently, each GCC i386 target always uses the same register - numbering scheme across all its supported debugging formats - i.e. SDB (COFF), stabs and DWARF 2. This is because - gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the - DBX_REGISTER_NUMBER macro which is defined by each target's - respective config header in a manner independent of the requested - output debugging format. + /* XXX: index == 4 is always invalid */ + if (havesib && (index != 4 || scale != 0)) + { + regcache_raw_read (irp->regcache, index, (gdb_byte *) & tmpu32); + *addr += tmpu32 << scale; + } + } + else + { + /* 16 bits */ + switch (irp->mod) + { + case 0: + if (irp->rm == 6) + { + if (target_read_memory + (irp->addr, (gdb_byte *) & tmpu16, 2)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading " + "memory at addr 0x%s len = 2.\n"), + paddr_nz (irp->addr)); + return -1; + } + irp->addr += 2; + *addr = (int16_t) tmpu16; + irp->rm = 0; + goto no_rm; + } + else + { + *addr = 0; + } + break; + case 1: + if (target_read_memory (irp->addr, &tmpu8, 1)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading memory " + "at addr 0x%s len = 1.\n"), + paddr_nz (irp->addr)); + return -1; + } + irp->addr++; + *addr = (int8_t) tmpu8; + break; + case 2: + if (target_read_memory (irp->addr, (gdb_byte *) & tmpu16, 2)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading memory " + "at addr 0x%s len = 2.\n"), + paddr_nz (irp->addr)); + return -1; + } + irp->addr += 2; + *addr = (int16_t) tmpu16; + break; + } - This does not match the arrangement below, which presumes that - the SDB and stabs numbering schemes differ from the DWARF and - DWARF 2 ones. The reason for this arrangement is that it is - likely to get the numbering scheme for the target's - default/native debug format right. For targets where GCC is the - native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for - targets where the native toolchain uses a different numbering - scheme for a particular debug format (stabs-in-ELF on Solaris) - the defaults below will have to be overridden, like - i386_elf_init_abi() does. */ + switch (irp->rm) + { + case 0: + regcache_raw_read (irp->regcache, I386_EBX_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + regcache_raw_read (irp->regcache, I386_ESI_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + break; + case 1: + regcache_raw_read (irp->regcache, I386_EBX_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + regcache_raw_read (irp->regcache, I386_EDI_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + break; + case 2: + regcache_raw_read (irp->regcache, I386_EBP_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + regcache_raw_read (irp->regcache, I386_ESI_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + break; + case 3: + regcache_raw_read (irp->regcache, I386_EBP_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + regcache_raw_read (irp->regcache, I386_EDI_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + break; + case 4: + regcache_raw_read (irp->regcache, I386_ESI_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + break; + case 5: + regcache_raw_read (irp->regcache, I386_EDI_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + break; + case 6: + regcache_raw_read (irp->regcache, I386_EBP_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + break; + case 7: + regcache_raw_read (irp->regcache, I386_EBX_REGNUM, + (gdb_byte *) & tmpu32); + *addr += tmpu32; + break; + } + *addr &= 0xffff; + } - /* Use the dbx register numbering scheme for stabs and COFF. */ - set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); - set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); +no_rm: + return 0; +} - /* Use the SVR4 register numbering scheme for DWARF 2. */ - set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); +/* Record the value of the memory that willbe changed in current instruction + to "record_arch_list". + Return -1 if something wrong. */ - /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to - be in use on any of the supported i386 targets. */ +static int +i386_record_lea_modrm (struct i386_record_s *irp) +{ + uint32_t addr; - set_gdbarch_print_float_info (gdbarch, i387_print_float_info); + if (irp->override) + { + if (record_debug) + printf_unfiltered (_("Process record ignores the memory change " + "of instruction at address 0x%s because it " + "can't get the value of the segment register.\n"), + paddr_nz (irp->addr)); + return 0; + } - set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); + if (i386_record_lea_modrm_addr (irp, &addr)) + return -1; - /* Call dummy code. */ - set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); + if (record_arch_list_add_mem (addr, 1 << irp->ot)) + return -1; - set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); - set_gdbarch_register_to_value (gdbarch, i386_register_to_value); - set_gdbarch_value_to_register (gdbarch, i386_value_to_register); + return 0; +} - set_gdbarch_return_value (gdbarch, i386_return_value); +/* Parse the current instruction and record the values of the registers and + memory that will be changed in current instruction to "record_arch_list". + Return -1 if something wrong. */ - set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); +static int +i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, + CORE_ADDR addr) +{ + int prefixes = 0; + uint8_t tmpu8; + uint16_t tmpu16; + uint32_t tmpu32; + uint32_t opcode; + struct i386_record_s ir; + + bzero (&ir, sizeof (struct i386_record_s)); + ir.regcache = regcache; + ir.addr = addr; + ir.aflag = 1; + ir.dflag = 1; + + if (record_debug > 1) + fprintf_unfiltered (gdb_stdlog, "Process record: i386_process_record " + "addr = 0x%s\n", + paddr_nz (ir.addr)); + + /* prefixes */ + while (1) + { + if (target_read_memory (ir.addr, &tmpu8, 1)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading memory at " + "addr 0x%s len = 1.\n"), + paddr_nz (ir.addr)); + return -1; + } + ir.addr++; + switch (tmpu8) + { + case 0xf3: + prefixes |= PREFIX_REPZ; + break; + case 0xf2: + prefixes |= PREFIX_REPNZ; + break; + case 0xf0: + prefixes |= PREFIX_LOCK; + break; + case 0x2e: + ir.override = I386_CS_REGNUM; + break; + case 0x36: + ir.override = I386_SS_REGNUM; + break; + case 0x3e: + ir.override = I386_DS_REGNUM; + break; + case 0x26: + ir.override = I386_ES_REGNUM; + break; + case 0x64: + ir.override = I386_FS_REGNUM; + break; + case 0x65: + ir.override = I386_GS_REGNUM; + break; + case 0x66: + prefixes |= PREFIX_DATA; + break; + case 0x67: + prefixes |= PREFIX_ADDR; + break; + default: + goto out_prefixes; + break; + } + } +out_prefixes: + if (prefixes & PREFIX_DATA) + ir.dflag ^= 1; + if (prefixes & PREFIX_ADDR) + ir.aflag ^= 1; + + /* now check op code */ + opcode = (uint32_t) tmpu8; +reswitch: + switch (opcode) + { + case 0x0f: + if (target_read_memory (ir.addr, &tmpu8, 1)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading memory at " + "addr 0x%s len = 1.\n"), + paddr_nz (ir.addr)); + return -1; + } + ir.addr++; + opcode = (uint16_t) tmpu8 | 0x0f00; + goto reswitch; + break; - /* Stack grows downward. */ - set_gdbarch_inner_than (gdbarch, core_addr_lessthan); + /* arith & logic */ + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0c: + case 0x0d: + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x18: + case 0x19: + case 0x1a: + case 0x1b: + case 0x1c: + case 0x1d: + case 0x20: + case 0x21: + case 0x22: + case 0x23: + case 0x24: + case 0x25: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + case 0x2c: + case 0x2d: + case 0x30: + case 0x31: + case 0x32: + case 0x33: + case 0x34: + case 0x35: + case 0x38: + case 0x39: + case 0x3a: + case 0x3b: + case 0x3c: + case 0x3d: + if (((opcode >> 3) & 7) != OP_CMPL) + { + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; - set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); - set_gdbarch_decr_pc_after_break (gdbarch, 1); - set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); + switch ((opcode >> 1) & 3) + { + /* OP Ev, Gv */ + case 0: + if (i386_record_modrm (&ir)) + return -1; + if (ir.mod != 3) + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + else + { + if (ir.ot == OT_BYTE) + ir.rm &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + break; + /* OP Gv, Ev */ + case 1: + if (i386_record_modrm (&ir)) + return -1; + if (ir.ot == OT_BYTE) + ir.reg &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + break; + /* OP A, Iv */ + case 2: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + break; + } + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; - set_gdbarch_frame_args_skip (gdbarch, 8); + /* GRP1 */ + case 0x80: + case 0x81: + case 0x82: + case 0x83: + if (i386_record_modrm (&ir)) + return -1; - /* Wire in the MMX registers. */ - set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs); - set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); - set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); + if (ir.reg != OP_CMPL) + { + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; - set_gdbarch_print_insn (gdbarch, i386_print_insn); + if (ir.mod != 3) + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + else + { + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; - set_gdbarch_dummy_id (gdbarch, i386_dummy_id); + /* inv */ + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + /* dec */ + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: + if (record_arch_list_add_reg (ir.regcache, opcode & 7)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; - set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); + /* GRP3 */ + case 0xf6: + case 0xf7: + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; + if (i386_record_modrm (&ir)) + return -1; - /* Add the i386 register groups. */ - i386_add_reggroups (gdbarch); - set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p); + switch (ir.reg) + { + /* test */ + case 0: + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + /* not */ + case 2: + if (ir.mod != 3) + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + else + { + if (ir.ot == OT_BYTE) + ir.rm &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + break; + /* neg */ + case 3: + if (ir.mod != 3) + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + else + { + if (ir.ot == OT_BYTE) + ir.rm &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + /* mul */ + case 4: + /* imul */ + case 5: + /* div */ + case 6: + /* idiv */ + case 7: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + if (ir.ot != OT_BYTE) + { + if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + default: + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + break; + } + break; + + /* GRP4 */ + case 0xfe: + /* GRP5 */ + case 0xff: + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; + if (i386_record_modrm (&ir)) + return -1; + if (ir.reg >= 2 && opcode == 0xfe) + { + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + + switch (ir.reg) + { + /* inc */ + case 0: + /* dec */ + case 1: + if (ir.mod != 3) + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + else + { + if (ir.ot == OT_BYTE) + ir.rm &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + /* call */ + case 2: + /* push */ + case 6: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + regcache_raw_read (ir.regcache, I386_ESP_REGNUM, + (gdb_byte *) & tmpu32); + if (record_arch_list_add_mem + ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1)))) + return -1; + break; + /* lcall */ + case 3: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM)) + return -1; + regcache_raw_read (ir.regcache, I386_ESP_REGNUM, + (gdb_byte *) & tmpu32); + if (record_arch_list_add_mem + ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2)))) + return -1; + break; + /* jmp */ + case 4: + /* ljmp */ + case 5: + break; + default: + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + break; + } + break; + + /* test */ + case 0x84: + case 0x85: + case 0xa8: + case 0xa9: + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* CWDE/CBW */ + case 0x98: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + break; + + /* CDQ/CWD */ + case 0x99: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM)) + return -1; + break; + + /* imul */ + case 0x0faf: + case 0x69: + case 0x6b: + ir.ot = ir.dflag + OT_WORD; + if (i386_record_modrm (&ir)) + return -1; + if (ir.ot == OT_BYTE) + ir.reg &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* xadd */ + case 0x0fc0: + case 0x0fc1: + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; + if (i386_record_modrm (&ir)) + return -1; + if (ir.mod == 3) + { + if (ir.ot == OT_BYTE) + ir.reg &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + if (ir.ot == OT_BYTE) + ir.rm &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + else + { + if (i386_record_lea_modrm (&ir)) + return -1; + if (ir.ot == OT_BYTE) + ir.reg &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* cmpxchg */ + case 0x0fb0: + case 0x0fb1: + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; + if (i386_record_modrm (&ir)) + return -1; + if (ir.mod == 3) + { + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + if (ir.ot == OT_BYTE) + ir.reg &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + } + else + { + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + if (i386_record_lea_modrm (&ir)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* cmpxchg8b */ + case 0x0fc7: + if (i386_record_modrm (&ir)) + return -1; + if (ir.mod == 3) + { + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM)) + return -1; + if (i386_record_lea_modrm (&ir)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* push */ + case 0x50: + case 0x51: + case 0x52: + case 0x53: + case 0x54: + case 0x55: + case 0x56: + case 0x57: + case 0x68: + case 0x6a: + /* push es */ + case 0x06: + /* push cs */ + case 0x0e: + /* push ss */ + case 0x16: + /* push ds */ + case 0x1e: + /* push fs */ + case 0x0fa0: + /* push gs */ + case 0x0fa8: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + regcache_raw_read (ir.regcache, I386_ESP_REGNUM, + (gdb_byte *) & tmpu32); + if (record_arch_list_add_mem + ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1)))) + return -1; + break; + + /* pop */ + case 0x58: + case 0x59: + case 0x5a: + case 0x5b: + case 0x5c: + case 0x5d: + case 0x5e: + case 0x5f: + ir.ot = ir.dflag + OT_WORD; + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (ir.ot == OT_BYTE) + opcode &= 0x3; + if (record_arch_list_add_reg (ir.regcache, opcode & 0x7)) + return -1; + break; + + /* pusha */ + case 0x60: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + regcache_raw_read (ir.regcache, I386_ESP_REGNUM, + (gdb_byte *) & tmpu32); + if (record_arch_list_add_mem + ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 4)), (1 << (ir.dflag + 4)))) + return -1; + break; + + /* popa */ + case 0x61: + for (tmpu8 = I386_EAX_REGNUM; tmpu8 <= I386_EDI_REGNUM; tmpu8++) + { + if (record_arch_list_add_reg (ir.regcache, tmpu8)) + return -1; + } + break; + + /* pop */ + case 0x8f: + ir.ot = ir.dflag + OT_WORD; + if (i386_record_modrm (&ir)) + return -1; + if (ir.mod == 3) + { + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + else + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + break; + + /* enter */ + case 0xc8: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM)) + return -1; + regcache_raw_read (ir.regcache, I386_ESP_REGNUM, + (gdb_byte *) & tmpu32); + if (record_arch_list_add_mem + ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1)))) + return -1; + break; + + /* leave */ + case 0xc9: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EBP_REGNUM)) + return -1; + break; + + /* pop es */ + case 0x07: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_ES_REGNUM)) + return -1; + break; + + /* pop ss */ + case 0x17: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_SS_REGNUM)) + return -1; + break; + + /* pop ds */ + case 0x1f: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_DS_REGNUM)) + return -1; + break; + + /* pop fs */ + case 0x0fa1: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_FS_REGNUM)) + return -1; + break; + + /* pop gs */ + case 0x0fa9: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_GS_REGNUM)) + return -1; + break; + + /* mov */ + case 0x88: + case 0x89: + case 0xc6: + case 0xc7: + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; + + if (i386_record_modrm (&ir)) + return -1; + + if (ir.mod != 3) + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + else + { + if (ir.ot == OT_BYTE) + ir.rm &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + /* mov */ + case 0x8a: + case 0x8b: + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; + + if (i386_record_modrm (&ir)) + return -1; + + if (ir.ot == OT_BYTE) + ir.reg &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* mov seg */ + case 0x8e: + if (i386_record_modrm (&ir)) + return -1; + + switch (ir.reg) + { + case 0: + tmpu8 = I386_ES_REGNUM; + break; + case 2: + tmpu8 = I386_SS_REGNUM; + break; + case 3: + tmpu8 = I386_DS_REGNUM; + break; + case 4: + tmpu8 = I386_FS_REGNUM; + break; + case 5: + tmpu8 = I386_GS_REGNUM; + break; + default: + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + break; + } + if (record_arch_list_add_reg (ir.regcache, tmpu8)) + return -1; + + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* mov seg */ + case 0x8c: + if (i386_record_modrm (&ir)) + return -1; + if (ir.reg > 5) + { + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + + if (ir.mod == 3) + { + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + else + { + ir.ot = OT_WORD; + if (i386_record_lea_modrm (&ir)) + return -1; + } + + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* movzbS */ + case 0x0fb6: + /* movzwS */ + case 0x0fb7: + /* movsbS */ + case 0x0fbe: + /* movswS */ + case 0x0fbf: + if (i386_record_modrm (&ir)) + return -1; + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + break; + + /* lea */ + case 0x8d: + if (i386_record_modrm (&ir)) + return -1; + if (ir.mod == 3) + { + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + + ir.ot = ir.dflag; + if (ir.ot == OT_BYTE) + ir.reg &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + break; + + /* mov EAX */ + case 0xa0: + case 0xa1: + /* xlat */ + case 0xd7: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + break; + + /* mov EAX */ + case 0xa2: + case 0xa3: + { + uint32_t addr; + + if (ir.override) + { + if (record_debug) + printf_unfiltered (_("Process record ignores the memory change " + "of instruction at address 0x%s because " + "it can't get the value of the segment " + "register.\n"), + paddr_nz (ir.addr)); + } + else + { + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; + if (ir.aflag) + { + if (target_read_memory + (ir.addr, (gdb_byte *) & addr, 4)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading " + "memory at addr 0x%s len = 4.\n"), + paddr_nz (ir.addr)); + return -1; + } + ir.addr += 4; + } + else + { + if (target_read_memory + (ir.addr, (gdb_byte *) & tmpu16, 4)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading " + "memory at addr 0x%s len = 4.\n"), + paddr_nz (ir.addr)); + return -1; + } + ir.addr += 2; + addr = tmpu16; + } + if (record_arch_list_add_mem (addr, 1 << ir.ot)) + return -1; + } + } + break; + + /* mov R, Ib */ + case 0xb0: + case 0xb1: + case 0xb2: + case 0xb3: + case 0xb4: + case 0xb5: + case 0xb6: + case 0xb7: + if (record_arch_list_add_reg (ir.regcache, (opcode & 0x7) & 0x3)) + return -1; + break; + + /* mov R, Iv */ + case 0xb8: + case 0xb9: + case 0xba: + case 0xbb: + case 0xbc: + case 0xbd: + case 0xbe: + case 0xbf: + if (record_arch_list_add_reg (ir.regcache, opcode & 0x7)) + return -1; + break; + + /* xchg R, EAX */ + case 0x91: + case 0x92: + case 0x93: + case 0x94: + case 0x95: + case 0x96: + case 0x97: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, opcode & 0x7)) + return -1; + break; + + /* xchg Ev, Gv */ + case 0x86: + case 0x87: + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; + + if (i386_record_modrm (&ir)) + return -1; + + if (ir.mod == 3) + { + if (ir.ot == OT_BYTE) + ir.rm &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + else + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + + if (ir.ot == OT_BYTE) + ir.reg &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + break; + + /* les Gv */ + case 0xc4: + /* lds Gv */ + case 0xc5: + /* lss Gv */ + case 0x0fb2: + /* lfs Gv */ + case 0x0fb4: + /* lgs Gv */ + case 0x0fb5: + if (i386_record_modrm (&ir)) + return -1; + if (ir.mod == 3) + { + if (opcode > 0xff) + ir.addr -= 3; + else + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + + switch (opcode) + { + /* les Gv */ + case 0xc4: + tmpu8 = I386_ES_REGNUM; + break; + /* lds Gv */ + case 0xc5: + tmpu8 = I386_DS_REGNUM; + break; + /* lss Gv */ + case 0x0fb2: + tmpu8 = I386_SS_REGNUM; + break; + /* lfs Gv */ + case 0x0fb4: + tmpu8 = I386_FS_REGNUM; + break; + /* lgs Gv */ + case 0x0fb5: + tmpu8 = I386_GS_REGNUM; + break; + } + if (record_arch_list_add_reg (ir.regcache, tmpu8)) + return -1; + + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + break; + + /* shifts */ + case 0xc0: + case 0xc1: + case 0xd0: + case 0xd1: + case 0xd2: + case 0xd3: + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; + + if (i386_record_modrm (&ir)) + return -1; + + if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + else + { + if (ir.ot == OT_BYTE) + ir.rm &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + case 0x0fa4: + case 0x0fa5: + case 0x0fac: + case 0x0fad: + if (i386_record_modrm (&ir)) + return -1; + if (ir.mod == 3) + { + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + else + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + break; + + /* floats */ + /* It just record the memory change of instrcution. */ + case 0xd8: + case 0xd9: + case 0xda: + case 0xdb: + case 0xdc: + case 0xdd: + case 0xde: + case 0xdf: + if (i386_record_modrm (&ir)) + return -1; + ir.reg |= ((opcode & 7) << 3); + if (ir.mod != 3) + { + /* memory */ + uint32_t addr; + + if (i386_record_lea_modrm_addr (&ir, &addr)) + return -1; + switch (ir.reg) + { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + case 0x10: + case 0x11: + case 0x12: + case 0x13: + case 0x14: + case 0x15: + case 0x16: + case 0x17: + case 0x20: + case 0x21: + case 0x22: + case 0x23: + case 0x24: + case 0x25: + case 0x26: + case 0x27: + case 0x30: + case 0x31: + case 0x32: + case 0x33: + case 0x34: + case 0x35: + case 0x36: + case 0x37: + break; + case 0x08: + case 0x0a: + case 0x0b: + case 0x18: + case 0x19: + case 0x1a: + case 0x1b: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + case 0x38: + case 0x39: + case 0x3a: + case 0x3b: + switch (ir.reg & 7) + { + case 0: + break; + case 1: + switch (ir.reg >> 4) + { + case 0: + if (record_arch_list_add_mem (addr, 4)) + return -1; + break; + case 2: + if (record_arch_list_add_mem (addr, 8)) + return -1; + break; + case 3: + default: + if (record_arch_list_add_mem (addr, 2)) + return -1; + break; + } + break; + default: + switch (ir.reg >> 4) + { + case 0: + case 1: + if (record_arch_list_add_mem (addr, 4)) + return -1; + break; + case 2: + if (record_arch_list_add_mem (addr, 8)) + return -1; + break; + case 3: + default: + if (record_arch_list_add_mem (addr, 2)) + return -1; + break; + } + break; + } + break; + case 0x0c: + case 0x0d: + case 0x1d: + case 0x2c: + case 0x3c: + case 0x3d: + break; + case 0x0e: + if (ir.dflag) + { + if (record_arch_list_add_mem (addr, 28)) + return -1; + } + else + { + if (record_arch_list_add_mem (addr, 14)) + return -1; + } + break; + case 0x0f: + case 0x2f: + if (record_arch_list_add_mem (addr, 2)) + return -1; + break; + case 0x1f: + case 0x3e: + if (record_arch_list_add_mem (addr, 10)) + return -1; + break; + case 0x2e: + if (ir.dflag) + { + if (record_arch_list_add_mem (addr, 28)) + return -1; + addr += 28; + } + else + { + if (record_arch_list_add_mem (addr, 14)) + return -1; + addr += 14; + } + if (record_arch_list_add_mem (addr, 80)) + return -1; + break; + case 0x3f: + if (record_arch_list_add_mem (addr, 8)) + return -1; + break; + default: + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + break; + } + } + break; + + /* string ops */ + /* movsS */ + case 0xa4: + case 0xa5: + /* stosS */ + case 0xaa: + case 0xab: + /* insS */ + case 0x6c: + case 0x6d: + { + uint32_t addr; + + if ((opcode & 1) == 0) + ir.ot = OT_BYTE; + else + ir.ot = ir.dflag + OT_WORD; + if (opcode == 0xa4 || opcode == 0xa5) + { + if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM)) + return -1; + + regcache_raw_read (ir.regcache, I386_EDI_REGNUM, + (gdb_byte *) & addr); + if (!ir.aflag) + { + addr &= 0xffff; + /* addr += ((uint32_t)read_register (I386_ES_REGNUM)) << 4; */ + if (record_debug) + printf_unfiltered (_("Process record ignores the memory change " + "of instruction at address 0x%s because " + "it can't get the value of the segment " + "register.\n"), + paddr_nz (ir.addr)); + } + + if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) + { + uint32_t count; + + regcache_raw_read (ir.regcache, I386_ECX_REGNUM, + (gdb_byte *) & count); + if (!ir.aflag) + count &= 0xffff; + + regcache_raw_read (ir.regcache, I386_EFLAGS_REGNUM, + (gdb_byte *) & tmpu32); + if ((tmpu32 >> 10) & 0x1) + addr -= (count - 1) * (1 << ir.ot); + + if (ir.aflag) + { + if (record_arch_list_add_mem (addr, count * (1 << ir.ot))) + return -1; + } + + if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) + return -1; + } + else + { + if (ir.aflag) + { + if (record_arch_list_add_mem (addr, 1 << ir.ot)) + return -1; + } + } + } + break; + + /* lodsS */ + case 0xac: + case 0xad: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM)) + return -1; + if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) + { + if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) + return -1; + } + break; + + /* outsS */ + case 0x6e: + case 0x6f: + if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM)) + return -1; + if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) + { + if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) + return -1; + } + break; + + /* scasS */ + case 0xae: + case 0xaf: + if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM)) + return -1; + if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) + { + if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* cmpsS */ + case 0xa6: + case 0xa7: + if (record_arch_list_add_reg (ir.regcache, I386_EDI_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_ESI_REGNUM)) + return -1; + if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) + { + if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* port I/O */ + case 0xe4: + case 0xe5: + case 0xec: + case 0xed: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + break; + + case 0xe6: + case 0xe7: + case 0xee: + case 0xef: + break; + + /* control */ + /* ret im */ + case 0xc2: + /* ret */ + case 0xc3: + /* lret im */ + case 0xca: + /* lret */ + case 0xcb: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM)) + return -1; + break; + + /* iret */ + case 0xcf: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* call im */ + case 0xe8: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + regcache_raw_read (ir.regcache, I386_ESP_REGNUM, + (gdb_byte *) & tmpu32); + if (record_arch_list_add_mem + ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1)))) + return -1; + break; + + /* lcall im */ + case 0x9a: + if (record_arch_list_add_reg (ir.regcache, I386_CS_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + regcache_raw_read (ir.regcache, I386_ESP_REGNUM, + (gdb_byte *) & tmpu32); + if (record_arch_list_add_mem + ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 2)), (1 << (ir.dflag + 2)))) + return -1; + break; + + /* jmp im */ + case 0xe9: + /* ljmp im */ + case 0xea: + /* jmp Jb */ + case 0xeb: + /* jcc Jb */ + case 0x70: + case 0x71: + case 0x72: + case 0x73: + case 0x74: + case 0x75: + case 0x76: + case 0x77: + case 0x78: + case 0x79: + case 0x7a: + case 0x7b: + case 0x7c: + case 0x7d: + case 0x7e: + case 0x7f: + /* jcc Jv */ + case 0x0f80: + case 0x0f81: + case 0x0f82: + case 0x0f83: + case 0x0f84: + case 0x0f85: + case 0x0f86: + case 0x0f87: + case 0x0f88: + case 0x0f89: + case 0x0f8a: + case 0x0f8b: + case 0x0f8c: + case 0x0f8d: + case 0x0f8e: + case 0x0f8f: + break; + + /* setcc Gv */ + case 0x0f90: + case 0x0f91: + case 0x0f92: + case 0x0f93: + case 0x0f94: + case 0x0f95: + case 0x0f96: + case 0x0f97: + case 0x0f98: + case 0x0f99: + case 0x0f9a: + case 0x0f9b: + case 0x0f9c: + case 0x0f9d: + case 0x0f9e: + case 0x0f9f: + ir.ot = OT_BYTE; + if (i386_record_modrm (&ir)) + return -1; + if (ir.mod == 3) + { + if (record_arch_list_add_reg (ir.regcache, ir.rm & 0x3)) + return -1; + } + else + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + break; + + /* cmov Gv, Ev */ + case 0x0f40: + case 0x0f41: + case 0x0f42: + case 0x0f43: + case 0x0f44: + case 0x0f45: + case 0x0f46: + case 0x0f47: + case 0x0f48: + case 0x0f49: + case 0x0f4a: + case 0x0f4b: + case 0x0f4c: + case 0x0f4d: + case 0x0f4e: + case 0x0f4f: + if (i386_record_modrm (&ir)) + return -1; + if (ir.dflag == OT_BYTE) + ir.reg &= 0x3; + if (record_arch_list_add_reg (ir.regcache, ir.reg & 0x3)) + return -1; + break; + + /* flags */ + /* pushf */ + case 0x9c: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + regcache_raw_read (ir.regcache, I386_ESP_REGNUM, + (gdb_byte *) & tmpu32); + if (record_arch_list_add_mem + ((CORE_ADDR) tmpu32 - (1 << (ir.dflag + 1)), (1 << (ir.dflag + 1)))) + return -1; + break; + + /* popf */ + case 0x9d: + if (record_arch_list_add_reg (ir.regcache, I386_ESP_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* sahf */ + case 0x9e: + /* cmc */ + case 0xf5: + /* clc */ + case 0xf8: + /* stc */ + case 0xf9: + /* cld */ + case 0xfc: + /* std */ + case 0xfd: + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* lahf */ + case 0x9f: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + break; + + /* bit operations */ + /* bt/bts/btr/btc Gv, im */ + case 0x0fba: + /* bts */ + case 0x0fab: + /* btr */ + case 0x0fb3: + /* btc */ + case 0x0fbb: + ir.ot = ir.dflag + OT_WORD; + if (i386_record_modrm (&ir)) + return -1; + if (ir.reg < 4) + { + ir.addr -= 3; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + ir.reg -= 4; + if (ir.reg != 0) + { + if (ir.mod != 3) + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + else + { + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* bt Gv, Ev */ + case 0x0fa3: + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* bsf */ + case 0x0fbc: + /* bsr */ + case 0x0fbd: + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* bcd */ + /* daa */ + case 0x27: + /* das */ + case 0x2f: + /* aaa */ + case 0x37: + /* aas */ + case 0x3f: + /* aam */ + case 0xd4: + /* aad */ + case 0xd5: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* misc */ + /* nop */ + case 0x90: + if (prefixes & PREFIX_LOCK) + { + ir.addr -= 1; + goto no_support; + } + break; + + /* fwait */ + /* XXX */ + case 0x9b: + printf_unfiltered (_("Process record doesn't support instruction " + "fwait.\n")); + ir.addr -= 1; + goto no_support; + break; + + /* int3 */ + /* XXX */ + case 0xcc: + printf_unfiltered (_("Process record doesn't support instruction " + "int3.\n")); + ir.addr -= 1; + goto no_support; + break; + + /* int */ + /* XXX */ + case 0xcd: + { + int ret; + if (target_read_memory (ir.addr, &tmpu8, 1)) + { + if (record_debug) + printf_unfiltered (_("Process record: error reading memory " + "at addr 0x%s len = 1.\n"), + paddr_nz (ir.addr)); + return -1; + } + ir.addr++; + if (tmpu8 != 0x80 + || gdbarch_tdep (gdbarch)->i386_intx80_record == NULL) + { + printf_unfiltered (_("Process record doesn't support " + "instruction int 0x%02x.\n"), + tmpu8); + ir.addr -= 2; + goto no_support; + } + ret = gdbarch_tdep (gdbarch)->i386_intx80_record (ir.regcache); + if (ret) + return ret; + } + break; + + /* into */ + /* XXX */ + case 0xce: + printf_unfiltered (_("Process record doesn't support " + "instruction into.\n")); + ir.addr -= 1; + goto no_support; + break; + + /* cli */ + case 0xfa: + /* sti */ + case 0xfb: + break; + + /* bound */ + case 0x62: + printf_unfiltered (_("Process record doesn't support " + "instruction bound.\n")); + ir.addr -= 1; + goto no_support; + break; + + /* bswap reg */ + case 0x0fc8: + case 0x0fc9: + case 0x0fca: + case 0x0fcb: + case 0x0fcc: + case 0x0fcd: + case 0x0fce: + case 0x0fcf: + if (record_arch_list_add_reg (ir.regcache, opcode & 7)) + return -1; + break; + + /* salc */ + case 0xd6: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* loopnz */ + case 0xe0: + /* loopz */ + case 0xe1: + /* loop */ + case 0xe2: + /* jecxz */ + case 0xe3: + if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) + return -1; + break; + + /* wrmsr */ + case 0x0f30: + printf_unfiltered (_("Process record doesn't support " + "instruction wrmsr.\n")); + ir.addr -= 2; + goto no_support; + break; + + /* rdmsr */ + case 0x0f32: + printf_unfiltered (_("Process record doesn't support " + "instruction rdmsr.\n")); + ir.addr -= 2; + goto no_support; + break; + + /* rdtsc */ + case 0x0f31: + printf_unfiltered (_("Process record doesn't support " + "instruction rdtsc.\n")); + ir.addr -= 2; + goto no_support; + break; + + /* sysenter */ + case 0x0f34: + { + int ret; + if (gdbarch_tdep (gdbarch)->i386_sysenter_record == NULL) + { + printf_unfiltered (_("Process record doesn't support " + "instruction sysenter.\n")); + ir.addr -= 2; + goto no_support; + } + ret = gdbarch_tdep (gdbarch)->i386_sysenter_record (ir.regcache); + if (ret) + return ret; + } + break; + + /* sysexit */ + case 0x0f35: + printf_unfiltered (_("Process record doesn't support " + "instruction sysexit.\n")); + ir.addr -= 2; + goto no_support; + break; + + /* cpuid */ + case 0x0fa2: + if (record_arch_list_add_reg (ir.regcache, I386_EAX_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_ECX_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EDX_REGNUM)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EBX_REGNUM)) + return -1; + break; + + /* hlt */ + case 0xf4: + printf_unfiltered (_("Process record doesn't support " + "instruction hlt.\n")); + ir.addr -= 1; + goto no_support; + break; + + case 0x0f00: + if (i386_record_modrm (&ir)) + return -1; + switch (ir.reg) + { + /* sldt */ + case 0: + /* str */ + case 1: + if (ir.mod == 3) + { + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + else + { + ir.ot = OT_WORD; + if (i386_record_lea_modrm (&ir)) + return -1; + } + break; + /* lldt */ + case 2: + /* ltr */ + case 3: + break; + /* verr */ + case 4: + /* verw */ + case 5: + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + default: + ir.addr -= 3; + opcode = opcode << 8 | ir.modrm; + goto no_support; + break; + } + break; + + case 0x0f01: + if (i386_record_modrm (&ir)) + return -1; + switch (ir.reg) + { + /* sgdt */ + case 0: + { + uint32_t addr; + + if (ir.mod == 3) + { + ir.addr -= 3; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + + if (ir.override) + { + if (record_debug) + printf_unfiltered (_("Process record ignores the memory " + "change of instruction at " + "address 0x%s because it can't get " + "the value of the segment " + "register.\n"), + paddr_nz (ir.addr)); + } + else + { + if (i386_record_lea_modrm_addr (&ir, &addr)) + return -1; + if (record_arch_list_add_mem (addr, 2)) + return -1; + addr += 2; + if (record_arch_list_add_mem (addr, 4)) + return -1; + } + } + break; + case 1: + if (ir.mod == 3) + { + switch (ir.rm) + { + /* monitor */ + case 0: + break; + /* mwait */ + case 1: + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + default: + ir.addr -= 3; + opcode = opcode << 8 | ir.modrm; + goto no_support; + break; + } + } + else + { + /* sidt */ + if (ir.override) + { + if (record_debug) + printf_unfiltered (_("Process record ignores the memory " + "change of instruction at " + "address 0x%s because it can't get " + "the value of the segment " + "register.\n"), + paddr_nz (ir.addr)); + } + else + { + uint32_t addr; + + if (i386_record_lea_modrm_addr (&ir, &addr)) + return -1; + if (record_arch_list_add_mem (addr, 2)) + return -1; + addr += 2; + if (record_arch_list_add_mem (addr, 4)) + return -1; + } + } + break; + /* lgdt */ + case 2: + /* lidt */ + case 3: + /* invlpg */ + case 7: + default: + if (ir.mod == 3) + { + ir.addr -= 3; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + break; + /* smsw */ + case 4: + if (ir.mod == 3) + { + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + else + { + ir.ot = OT_WORD; + if (i386_record_lea_modrm (&ir)) + return -1; + } + break; + /* lmsw */ + case 6: + break; + } + break; + + /* invd */ + case 0x0f08: + /* wbinvd */ + case 0x0f09: + break; + + /* arpl */ + case 0x63: + ir.ot = ir.dflag ? OT_LONG : OT_WORD; + if (i386_record_modrm (&ir)) + return -1; + if (ir.mod != 3) + { + if (i386_record_lea_modrm (&ir)) + return -1; + } + else + { + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + /* lar */ + case 0x0f02: + /* lsl */ + case 0x0f03: + if (i386_record_modrm (&ir)) + return -1; + if (record_arch_list_add_reg (ir.regcache, ir.reg)) + return -1; + if (record_arch_list_add_reg (ir.regcache, I386_EFLAGS_REGNUM)) + return -1; + break; + + case 0x0f18: + break; + + /* nop (multi byte) */ + case 0x0f19: + case 0x0f1a: + case 0x0f1b: + case 0x0f1c: + case 0x0f1d: + case 0x0f1e: + case 0x0f1f: + break; + + /* mov reg, crN */ + case 0x0f20: + /* mov crN, reg */ + case 0x0f22: + if (i386_record_modrm (&ir)) + return -1; + if ((ir.modrm & 0xc0) != 0xc0) + { + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + switch (ir.reg) + { + case 0: + case 2: + case 3: + case 4: + case 8: + if (opcode & 2) + { + } + else + { + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + break; + default: + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + break; + } + break; + + /* mov reg, drN */ + case 0x0f21: + /* mov drN, reg */ + case 0x0f23: + if (i386_record_modrm (&ir)) + return -1; + if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 + || ir.reg == 5 || ir.reg >= 8) + { + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + if (opcode & 2) + { + } + else + { + if (record_arch_list_add_reg (ir.regcache, ir.rm)) + return -1; + } + break; + + /* clts */ + case 0x0f06: + break; + + /* MMX/SSE/SSE2/PNI support */ + /* XXX */ + + default: + if (opcode > 0xff) + ir.addr -= 2; + else + ir.addr -= 1; + goto no_support; + break; + } + +/* In the future, Maybe still need to deal with need_dasm */ + if (record_arch_list_add_reg (ir.regcache, I386_EIP_REGNUM)) + return -1; + if (record_arch_list_add_end ()) + return -1; + + return 0; + +no_support: + printf_unfiltered (_("Process record doesn't support instruction 0x%02x " + "at address 0x%s.\n"), + (unsigned int) (opcode), paddr_nz (ir.addr)); + return -1; +} + + +static struct gdbarch * +i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +{ + struct gdbarch_tdep *tdep; + struct gdbarch *gdbarch; + + /* If there is already a candidate, use it. */ + arches = gdbarch_list_lookup_by_info (arches, &info); + if (arches != NULL) + return arches->gdbarch; + + /* Allocate space for the new architecture. */ + tdep = XCALLOC (1, struct gdbarch_tdep); + gdbarch = gdbarch_alloc (&info, tdep); + + /* General-purpose registers. */ + tdep->gregset = NULL; + tdep->gregset_reg_offset = NULL; + tdep->gregset_num_regs = I386_NUM_GREGS; + tdep->sizeof_gregset = 0; + + /* Floating-point registers. */ + tdep->fpregset = NULL; + tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; + + /* The default settings include the FPU registers, the MMX registers + and the SSE registers. This can be overridden for a specific ABI + by adjusting the members `st0_regnum', `mm0_regnum' and + `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers + will show up in the output of "info all-registers". Ideally we + should try to autodetect whether they are available, such that we + can prevent "info all-registers" from displaying registers that + aren't available. + + NOTE: kevinb/2003-07-13: ... if it's a choice between printing + [the SSE registers] always (even when they don't exist) or never + showing them to the user (even when they do exist), I prefer the + former over the latter. */ + + tdep->st0_regnum = I386_ST0_REGNUM; + + /* The MMX registers are implemented as pseudo-registers. Put off + calculating the register number for %mm0 until we know the number + of raw registers. */ + tdep->mm0_regnum = 0; + + /* I386_NUM_XREGS includes %mxcsr, so substract one. */ + tdep->num_xmm_regs = I386_NUM_XREGS - 1; + + tdep->jb_pc_offset = -1; + tdep->struct_return = pcc_struct_return; + tdep->sigtramp_start = 0; + tdep->sigtramp_end = 0; + tdep->sigtramp_p = i386_sigtramp_p; + tdep->sigcontext_addr = NULL; + tdep->sc_reg_offset = NULL; + tdep->sc_pc_offset = -1; + tdep->sc_sp_offset = -1; + + /* The format used for `long double' on almost all i386 targets is + the i387 extended floating-point format. In fact, of all targets + in the GCC 2.95 tree, only OSF/1 does it different, and insists + on having a `long double' that's not `long' at all. */ + set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); + + /* Although the i387 extended floating-point has only 80 significant + bits, a `long double' actually takes up 96, probably to enforce + alignment. */ + set_gdbarch_long_double_bit (gdbarch, 96); + + /* The default ABI includes general-purpose registers, + floating-point registers, and the SSE registers. */ + set_gdbarch_num_regs (gdbarch, I386_SSE_NUM_REGS); + set_gdbarch_register_name (gdbarch, i386_register_name); + set_gdbarch_register_type (gdbarch, i386_register_type); + + /* Register numbers of various important registers. */ + set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ + set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ + set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ + set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ + + /* NOTE: kettenis/20040418: GCC does have two possible register + numbering schemes on the i386: dbx and SVR4. These schemes + differ in how they number %ebp, %esp, %eflags, and the + floating-point registers, and are implemented by the arrays + dbx_register_map[] and svr4_dbx_register_map in + gcc/config/i386.c. GCC also defines a third numbering scheme in + gcc/config/i386.c, which it designates as the "default" register + map used in 64bit mode. This last register numbering scheme is + implemented in dbx64_register_map, and is used for AMD64; see + amd64-tdep.c. + + Currently, each GCC i386 target always uses the same register + numbering scheme across all its supported debugging formats + i.e. SDB (COFF), stabs and DWARF 2. This is because + gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the + DBX_REGISTER_NUMBER macro which is defined by each target's + respective config header in a manner independent of the requested + output debugging format. + + This does not match the arrangement below, which presumes that + the SDB and stabs numbering schemes differ from the DWARF and + DWARF 2 ones. The reason for this arrangement is that it is + likely to get the numbering scheme for the target's + default/native debug format right. For targets where GCC is the + native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for + targets where the native toolchain uses a different numbering + scheme for a particular debug format (stabs-in-ELF on Solaris) + the defaults below will have to be overridden, like + i386_elf_init_abi() does. */ + + /* Use the dbx register numbering scheme for stabs and COFF. */ + set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); + set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); + + /* Use the SVR4 register numbering scheme for DWARF 2. */ + set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); + + /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to + be in use on any of the supported i386 targets. */ + + set_gdbarch_print_float_info (gdbarch, i387_print_float_info); + + set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); + + /* Call dummy code. */ + set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); + + set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); + set_gdbarch_register_to_value (gdbarch, i386_register_to_value); + set_gdbarch_value_to_register (gdbarch, i386_value_to_register); + + set_gdbarch_return_value (gdbarch, i386_return_value); + + set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); + + /* Stack grows downward. */ + set_gdbarch_inner_than (gdbarch, core_addr_lessthan); + + set_gdbarch_breakpoint_from_pc (gdbarch, i386_breakpoint_from_pc); + set_gdbarch_decr_pc_after_break (gdbarch, 1); + set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); + + set_gdbarch_frame_args_skip (gdbarch, 8); + + /* Wire in the MMX registers. */ + set_gdbarch_num_pseudo_regs (gdbarch, i386_num_mmx_regs); + set_gdbarch_pseudo_register_read (gdbarch, i386_pseudo_register_read); + set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); + + set_gdbarch_print_insn (gdbarch, i386_print_insn); + + set_gdbarch_dummy_id (gdbarch, i386_dummy_id); + + set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); + + /* Add the i386 register groups. */ + i386_add_reggroups (gdbarch); + set_gdbarch_register_reggroup_p (gdbarch, i386_register_reggroup_p); /* Helper for function argument information. */ set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); @@ -2862,6 +5273,8 @@ i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_skip_permanent_breakpoint (gdbarch, i386_skip_permanent_breakpoint); + set_gdbarch_process_record (gdbarch, i386_process_record); + return gdbarch; } diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h index 6bebdfca2df..c73e7d94a0e 100644 --- a/gdb/i386-tdep.h +++ b/gdb/i386-tdep.h @@ -106,6 +106,12 @@ struct gdbarch_tdep /* ISA-specific data types. */ struct type *i386_mmx_type; struct type *i386_sse_type; + + /* Process record/replay target. */ + /* Parse intx80 args. */ + int (*i386_intx80_record) (struct regcache *regcache); + /* Parse sysenter args. */ + int (*i386_sysenter_record) (struct regcache *regcache); }; /* Floating-point registers. */