From: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Date: Fri, 12 Jun 2020 16:22:54 +0000 (-0400)
Subject: pan/mdg: Prefer type over regmode for schedule constraints
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ae2110e61fb0f8cf70dd9abf8c14df050381c05;p=mesa.git

pan/mdg: Prefer type over regmode for schedule constraints

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5443>
---

diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index 114a8de3211..9dee152c5e4 100644
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -198,12 +198,12 @@ mir_is_scalar(midgard_instruction *ains)
 
         /* Otherwise, check mode hazards */
         bool could_scalar = true;
+        unsigned szd = nir_alu_type_get_type_size(ains->dest_type);
         unsigned sz0 = nir_alu_type_get_type_size(ains->src_types[0]);
         unsigned sz1 = nir_alu_type_get_type_size(ains->src_types[1]);
 
         /* Only 16/32-bit can run on a scalar unit */
-        could_scalar &= ains->alu.reg_mode != midgard_reg_mode_8;
-        could_scalar &= ains->alu.reg_mode != midgard_reg_mode_64;
+        could_scalar &= (szd == 16) || (szd == 32);
 
         if (ains->src[0] != ~0)
                 could_scalar &= (sz0 == 16) || (sz0 == 32);