From: Gabe Black Date: Wed, 21 Feb 2007 00:25:50 +0000 (+0000) Subject: Update 50.vortex simple-timing for 8k blk_size X-Git-Tag: m5_2.0_beta3~179^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ae834446d3ee8b5ded269c21e88e6cdcdd6522f;p=gem5.git Update 50.vortex simple-timing for 8k blk_size --HG-- extra : convert_revision : 73f8c4f8f6da901021ea38e5ac053d905454a3ff --- diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini index 3e5bdc569..0e1a3c9f1 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.ini @@ -7,21 +7,6 @@ max_tick=0 output_file=cout progress_interval=0 -[exetrace] -intel_format=false -legion_lockstep=false -pc_symbol=true -print_cpseq=false -print_cycle=true -print_data=true -print_effaddr=true -print_fetchseq=false -print_iregs=false -print_opclass=true -print_thread=true -speculative=true -trace_system=client - [serialize] count=10 cycle=0 @@ -197,11 +182,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing egid=100 env= euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin output=cout @@ -223,14 +208,6 @@ type=PhysicalMemory file= latency=1 range=0:134217727 +zero=false port=system.membus.port[0] -[trace] -bufsize=0 -cycle=0 -dump_on_exit=false -file=cout -flags= -ignore= -start=0 - diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out index 9ecf4b55d..0dc85858d 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/config.out @@ -10,6 +10,7 @@ type=PhysicalMemory file= range=[0,134217727] latency=1 +zero=false [system] type=System @@ -26,11 +27,11 @@ responder_set=false [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex input=cin output=cout env= -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing system=system uid=100 euid=100 @@ -178,15 +179,6 @@ prefetch_use_cpu_id=true prefetch_data_accesses_only=false hit_latency=1 -[trace] -flags= -start=0 -cycle=0 -bufsize=0 -file=cout -dump_on_exit=false -ignore= - [stats] descriptions=true project_name=test @@ -204,25 +196,6 @@ dump_cycle=0 dump_period=0 ignore_events= -[random] -seed=1 - -[exetrace] -speculative=true -print_cycle=true -print_opclass=true -print_thread=true -print_effaddr=true -print_data=true -print_iregs=false -print_fetchseq=false -print_cpseq=false -print_reg_delta=false -pc_symbol=true -intel_format=false -legion_lockstep=false -trace_system=client - [statsreset] reset_cycle=0 diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt index ae340ffef..9a9778162 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/m5stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 471701 # Simulator instruction rate (inst/s) -host_mem_usage 255440 # Number of bytes of host memory used -host_seconds 187.33 # Real time elapsed on the host -host_tick_rate 6446013 # Simulator tick rate (ticks/s) +host_inst_rate 704446 # Simulator instruction rate (inst/s) +host_mem_usage 275648 # Number of bytes of host memory used +host_seconds 125.40 # Real time elapsed on the host +host_tick_rate 9716991 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88361899 # Number of instructions simulated -sim_seconds 0.001208 # Number of seconds simulated -sim_ticks 1207510003 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 20281385 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 3631.637073 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2631.637073 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20223321 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 210867375 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002863 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 58064 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 152803375 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 58064 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 4569.538784 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3569.538784 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14473602 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 649244640 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.009721 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 142081 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 507163640 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009721 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 142081 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 173.358930 # Average number of references to valid blocks. +sim_insts 88340674 # Number of instructions simulated +sim_seconds 0.001219 # Number of seconds simulated +sim_ticks 1218558003 # Number of ticks simulated +system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks. system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 34897068 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 4297.444428 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34696923 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 860112015 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005735 # miss rate for demand accesses -system.cpu.dcache.demand_misses 200145 # number of demand (read+write) misses +system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 659967015 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.005735 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 200145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.overall_accesses 34897068 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 4297.444428 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34696923 # number of overall hits -system.cpu.dcache.overall_miss_latency 860112015 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005735 # miss rate for overall accesses -system.cpu.dcache.overall_misses 200145 # number of overall misses +system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.dcache.overall_hits 34685672 # number of overall hits +system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_misses 204343 # number of overall misses system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 659967015 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.005735 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 200145 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.dcache.replacements 196049 # number of replacements -system.cpu.dcache.sampled_refs 200145 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 200247 # number of replacements +system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4056.501584 # Cycle average of tags in use -system.cpu.dcache.total_refs 34696923 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 28890000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 147135 # number of writebacks -system.cpu.icache.ReadReq_accesses 88361900 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 2933.039863 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 1933.039863 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 88285387 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 224415679 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000866 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 76513 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 147902679 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 76513 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1153.861265 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use +system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 147714 # number of writebacks +system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks. system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 88361900 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 2933.039863 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency -system.cpu.icache.demand_hits 88285387 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 224415679 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000866 # miss rate for demand accesses -system.cpu.icache.demand_misses 76513 # number of demand (read+write) misses +system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency +system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses +system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 147902679 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000866 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 76513 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.overall_accesses 88361900 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 2933.039863 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 88285387 # number of overall hits -system.cpu.icache.overall_miss_latency 224415679 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000866 # miss rate for overall accesses -system.cpu.icache.overall_misses 76513 # number of overall misses +system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.icache.overall_hits 88264239 # number of overall hits +system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses +system.cpu.icache.overall_misses 76436 # number of overall misses system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 147902679 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000866 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 76513 # number of overall MSHR misses +system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -135,64 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.icache.replacements 74468 # number of replacements -system.cpu.icache.sampled_refs 76513 # Sample count of references to valid blocks. +system.cpu.icache.replacements 74391 # number of replacements +system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1798.721885 # Cycle average of tags in use -system.cpu.icache.total_refs 88285387 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use +system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.l2cache.ReadReq_accesses 276658 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 3650.746755 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.771607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 108220 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 614924482 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.608831 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 168438 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 332289704 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608831 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 168438 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147135 # number of WriteReqNoAck|Writeback accesses(hits+misses) -system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146550 # number of WriteReqNoAck|Writeback hits -system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.003976 # miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_misses 585 # number of WriteReqNoAck|Writeback misses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.003976 # mshr miss rate for WriteReqNoAck|Writeback accesses -system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 585 # number of WriteReqNoAck|Writeback MSHR misses -system.cpu.l2cache.avg_blocked_cycles_no_mshrs # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles_no_targets # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.512545 # Average number of references to valid blocks. +system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits +system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses +system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses +system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses +system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses +system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked +system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks. system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 276658 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 3650.746755 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 108220 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 614924482 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.608831 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 168438 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 332289704 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.608831 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 168438 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.overall_accesses 423793 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 3638.111275 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 254770 # number of overall hits -system.cpu.l2cache.overall_miss_latency 614924482 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.398834 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 169023 # number of overall misses +system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency +system.cpu.l2cache.overall_hits 259377 # number of overall hits +system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 169116 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 332289704 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.397453 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 168438 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache @@ -204,17 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0 system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu.l2cache.replacements 135670 # number of replacements -system.cpu.l2cache.sampled_refs 168438 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 135910 # number of replacements +system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 30358.430189 # Cycle average of tags in use -system.cpu.l2cache.total_refs 254770 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 475381000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 115647 # number of writebacks +system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use +system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 115911 # number of writebacks system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1207510003 # number of cpu cycles simulated -system.cpu.num_insts 88361899 # Number of instructions executed -system.cpu.num_refs 35229376 # Number of memory references -system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls +system.cpu.numCycles 1218558003 # number of cpu cycles simulated +system.cpu.num_insts 88340674 # Number of instructions executed +system.cpu.num_refs 35224019 # Number of memory references +system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr index 87866a2a5..eb1796ead 100644 --- a/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr +++ b/tests/long/50.vortex/ref/alpha/linux/simple-timing/stderr @@ -1 +1,2 @@ +0: system.remote_gdb.listener: listening for remote gdb on port 7000 warn: Entering event queue @ 0. Starting simulation...