From: Marcelina Koƛcielnicka Date: Sat, 4 Jul 2020 22:55:38 +0000 (+0200) Subject: opt_expr: Fix crash on $mul optimization with more zeros removed than Y has. X-Git-Tag: working-ls180~413 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7afcb72c98620adaace7cc9622c4d577668f9426;p=yosys.git opt_expr: Fix crash on $mul optimization with more zeros removed than Y has. Fixes #2221. --- diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 1051a59f2..649ad83a6 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -1596,6 +1596,14 @@ skip_identity: log_debug("Removing low %d A and %d B bits from cell `%s' in module `%s'.\n", a_zeros, b_zeros, cell->name.c_str(), module->name.c_str()); + if (y_zeros >= GetSize(sig_y)) { + module->connect(sig_y, RTLIL::SigSpec(0, GetSize(sig_y))); + module->remove(cell); + + did_something = true; + goto next_cell; + } + if (a_zeros) { cell->setPort(ID::A, sig_a.extract_end(a_zeros)); cell->parameters[ID::A_WIDTH] = GetSize(sig_a) - a_zeros; diff --git a/tests/opt/bug2221.ys b/tests/opt/bug2221.ys new file mode 100644 index 000000000..8ac380243 --- /dev/null +++ b/tests/opt/bug2221.ys @@ -0,0 +1,16 @@ +read_verilog <