From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 27 Dec 2013 13:21:24 +0000 (+0100)
Subject: Fixed/improved opt_const $eq/$ne/$eqx/$nex handling
X-Git-Tag: yosys-0.2.0~226
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b02a44efbb81ce2c97dcb87f1d8ca016c14ba76;p=yosys.git

Fixed/improved opt_const $eq/$ne/$eqx/$nex handling
---

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 30d85588c..d84910ee1 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -166,6 +166,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					if (b.chunks[i].wire == NULL && b.chunks[i].data.bits[0] > RTLIL::State::S1)
 						continue;
 				}
+				if (a.chunks[i] == b.chunks[i])
+					continue;
 				new_a.append(a.chunks[i]);
 				new_b.append(b.chunks[i]);
 			}
@@ -177,7 +179,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				goto next_cell;
 			}
 
-			if (new_a.width != a.width) {
+			if (new_a.width < a.width || new_b.width < b.width) {
 				new_a.optimize();
 				new_b.optimize();
 				cell->connections["\\A"] = new_a;