From: Gabe Black Date: Sun, 8 Dec 2019 04:52:09 +0000 (-0800) Subject: riscv: Use a riscv specific GuestABI for riscv system calls. X-Git-Tag: v20.0.0.0~375 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b0cd2d59e4dd7a2ae4330ce3774f009daeb66b1;p=gem5.git riscv: Use a riscv specific GuestABI for riscv system calls. Change-Id: Ia6ac34dfb38b71eff7b573b3c9ce477fef0ef5f7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23453 Reviewed-by: Bobby R. Bruce Maintainer: Gabe Black Tested-by: kokoro --- diff --git a/src/arch/riscv/linux/process.cc b/src/arch/riscv/linux/process.cc index d5be09848..257fe7709 100644 --- a/src/arch/riscv/linux/process.cc +++ b/src/arch/riscv/linux/process.cc @@ -116,7 +116,7 @@ unameFunc32(SyscallDesc *desc, int callnum, ThreadContext *tc, Addr utsname) return 0; } -std::map> +std::map> RiscvLinuxProcess64::syscallDescs = { {0, { "io_setup" }}, {1, { "io_destroy" }}, @@ -448,7 +448,7 @@ std::map> {2011, { "getmainvars" }} }; -std::map> +std::map> RiscvLinuxProcess32::syscallDescs = { {0, { "io_setup" }}, {1, { "io_destroy" }}, diff --git a/src/arch/riscv/linux/process.hh b/src/arch/riscv/linux/process.hh index 521d645be..8d0d3ec85 100644 --- a/src/arch/riscv/linux/process.hh +++ b/src/arch/riscv/linux/process.hh @@ -55,7 +55,7 @@ class RiscvLinuxProcess64 : public RiscvProcess64 void syscall(ThreadContext *tc, Fault *fault) override; /// Array of syscall descriptors, indexed by call number. - static std::map> syscallDescs; + static std::map> syscallDescs; }; class RiscvLinuxProcess32 : public RiscvProcess32 @@ -75,7 +75,7 @@ class RiscvLinuxProcess32 : public RiscvProcess32 void syscall(ThreadContext *tc, Fault *fault) override; /// Array of syscall descriptors, indexed by call number. - static std::map> syscallDescs; + static std::map> syscallDescs; }; #endif // __RISCV_LINUX_PROCESS_HH__ diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc index a80f88cdc..9041bf316 100644 --- a/src/arch/riscv/process.cc +++ b/src/arch/riscv/process.cc @@ -266,3 +266,7 @@ RiscvProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret) tc->setIntReg(SyscallPseudoReturnReg, sysret.encodedValue()); } } + +const std::vector RiscvProcess::SyscallABI::ArgumentRegs = { + 10, 11, 12, 13, 14, 15, 16 +}; diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh index 933d6d19f..f3f8462b7 100644 --- a/src/arch/riscv/process.hh +++ b/src/arch/riscv/process.hh @@ -35,6 +35,7 @@ #include "mem/page_table.hh" #include "sim/process.hh" +#include "sim/syscall_abi.hh" class ObjectFile; class System; @@ -54,6 +55,36 @@ class RiscvProcess : public Process SyscallReturn return_value) override; virtual bool mmapGrowsDown() const override { return false; } + + //FIXME RISCV needs to handle 64 bit arguments in its 32 bit ISA. + struct SyscallABI : public GenericSyscallABI64 + { + static const std::vector ArgumentRegs; + }; +}; + +namespace GuestABI +{ + +template <> +struct Result +{ + static void + store(ThreadContext *tc, const SyscallReturn &ret) + { + if (ret.suppressed() || ret.needsRetry()) + return; + + if (ret.successful()) { + // no error + tc->setIntReg(RiscvISA::ReturnValueReg, ret.returnValue()); + } else { + // got an error, return details + tc->setIntReg(RiscvISA::ReturnValueReg, ret.encodedValue()); + } + } +}; + }; class RiscvProcess64 : public RiscvProcess