From: Claire Xen Date: Tue, 1 Dec 2020 11:31:34 +0000 (+0100) Subject: Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_defines X-Git-Tag: working-ls180~184 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b0cfd5c36af774ae255459d4ef0fa0934929902;p=yosys.git Merge pull request #2463 from georgerennie/fix_verilog_frontend_auto_defines Fix SYNTHESIS always being defined in Verilog frontend --- 7b0cfd5c36af774ae255459d4ef0fa0934929902