From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 4 Jun 2019 19:01:25 +0000 (-0700)
Subject: Add log_assert to ensure no loops
X-Git-Tag: working-ls180~1208^2~200
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b186740d33972612cfc9f2ebe31258edb0cca2b;p=yosys.git

Add log_assert to ensure no loops
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 4d45bb650..bf2f9f1bc 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -334,7 +334,21 @@ struct XAigerWriter
 
 			pool<RTLIL::Module*> abc_carry_modules;
 
-			toposort.sort();
+#if 0
+			toposort.analyze_loops = true;
+#endif
+			bool no_loops = toposort.sort();
+#if 0
+			unsigned i = 0;
+			for (auto &it : toposort.loops) {
+				log("  loop %d", i++);
+				for (auto cell : it)
+					log(" %s", log_id(cell));
+				log("\n");
+			}
+#endif
+			log_assert(no_loops);
+
 			for (auto cell_name : toposort.sorted) {
 				RTLIL::Cell *cell = module->cell(cell_name);
 				RTLIL::Module* box_module = module->design->module(cell->type);