From: lkcl <lkcl@web>
Date: Sun, 8 May 2022 15:49:26 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2303
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b26332e21d47a840a6eb1fa4316209e0bed3470;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index a70389608..9cc70584e 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -89,7 +89,8 @@ it.  ARM's SVE/SVE2 is critically flawed (lacking the Cray `setvl`
 instruction that makes a truly ubiquitous Vector ISA) in ways that
 will become apparent over time as adoption increases. In the meantime
 programmers are, in direct violation of ARM's advice on how to use SVE2,
-trying desperately to use it as if it was Packed SIMD NEON.  The advice
+trying desperately to understand it by applying their experience
+of Packed SIMD NEON.  The advice from ARM
 not to create SVE2 assembler that is hardcoded to fixed widths is being
 disregarded, in favour of writing *multiple identical implementations*
 of a function, each with a different hardware width, and compelling