From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Fri, 9 Jul 2004 15:50:27 +0000 (-0400)
Subject: when you add caches, dma commands within the state machine are delayed and cause... 
X-Git-Tag: m5_1.0_tutorial~252^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b2691d53725318810f78c712dbbe4733c319ef8;p=gem5.git

when you add caches, dma commands within the state machine are delayed and cause the state machine to exit until the dma comes back.  thus, all relevant code must be executed BEFORE going to do the dma code.

dev/ns_gige.cc:
    rearrange code so nothing gets skipped when "doing dma."

--HG--
extra : convert_revision : cca66885f45e7df1831e2d8ccaddf5ece7600b13
---

diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index f88fc507f..68a50bcce 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -1889,11 +1889,7 @@ NSGigE::txKick()
                 descDmaWrites++;
                 descDmaWrBytes += txDmaLen;
 
-                if (doTxDmaWrite())
-                    goto exit;
-
                 transmit();
-
                 txPacket = 0;
 
                 if (txHalt) {
@@ -1902,6 +1898,9 @@ NSGigE::txKick()
                     txHalt = false;
                 } else
                     txState = txAdvance;
+
+                if (doTxDmaWrite())
+                    goto exit;
             }
         } else {
             DPRINTF(EthernetSM, "this descriptor isn't done yet\n");