From: lkcl <lkcl@web>
Date: Mon, 20 Jun 2022 00:24:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b28cbff47afa18fc1f9b122de46c27c8786f196;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 68e37fbe2..ab57518a8 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -178,28 +178,9 @@ Example
 
 The vmsbf.m instruction takes a mask register as input and writes results to a mask register. The instruction writes a 1 to all active mask elements before the first source element that is a 1, then writes a 0 to that element and all following active elements. If there is no set bit in the source vector, then all active elements in the destination are written with a 1.
 
-pseudocode:
+Executable demo:
 
-    def sbf(rd, rs1, rs2):
-        rd = 0
-        # start setting if no predicate or if 1st predicate bit set
-        setting_mode = rs2 == x0 or (regs[rs2] & 1)
-        while i < XLEN:
-            bit = 1<<i
-            if rs2 != x0 and (regs[rs2] & bit):
-                # reset searching
-                setting_mode = False
-            if setting_mode:
-                if regs[rs1] & bit: # found a bit in rs1: stop setting rd
-                    setting_mode = False
-                else:
-                    regs[rd] |= bit
-            else if rs2 != x0: # searching mode
-                if (regs[rs2] & bit):
-                    setting_mode = True # back into "setting" mode
-            i += 1
-
-<https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/insns/vmsbf_m.h>
+[[!inline quick="yes" raw="yes" pages="openpower/sv/sbf.py"]]
 
 ## sifm