From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Wed, 10 Jun 2020 10:58:42 +0000 (+0200)
Subject: Autopep8
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b2f66053bd4000aaea5c3d6f496518818a2e138;p=gram.git

Autopep8
---

diff --git a/gram/frontend/wishbone.py b/gram/frontend/wishbone.py
index 59dfe41..bc92541 100644
--- a/gram/frontend/wishbone.py
+++ b/gram/frontend/wishbone.py
@@ -22,7 +22,8 @@ class gramWishbone(Peripheral, Elaboratable):
         self.bus = wishbone.Interface(addr_width=dram_addr_width,
                                       data_width=32, granularity=granularity)
 
-        map = MemoryMap(addr_width=dram_addr_width+log2_int(granularity)-1, data_width=granularity)
+        map = MemoryMap(addr_width=dram_addr_width +
+                        log2_int(granularity)-1, data_width=granularity)
         self.bus.memory_map = map
 
     def elaborate(self, platform):
@@ -30,7 +31,8 @@ class gramWishbone(Peripheral, Elaboratable):
 
         # Write datapath
         m.d.comb += [
-            self._port.wdata.valid.eq(self.bus.cyc & self.bus.stb & self.bus.we),
+            self._port.wdata.valid.eq(
+                self.bus.cyc & self.bus.stb & self.bus.we),
             self._port.wdata.data.eq(self.bus.dat_w),
             self._port.wdata.we.eq(self.bus.sel),
         ]
@@ -64,5 +66,4 @@ class gramWishbone(Peripheral, Elaboratable):
                     m.d.comb += self.bus.ack.eq(1)
                     m.next = "Send-Cmd"
 
-
         return m
diff --git a/gram/stream.py b/gram/stream.py
index c97e5aa..f0ce66d 100644
--- a/gram/stream.py
+++ b/gram/stream.py
@@ -153,7 +153,7 @@ class _UpConverter(Elaboratable):
             source_layout.append(("valid_token_count", bits_for(ratio)))
         self.source = source = Endpoint(source_layout)
         self.ratio = ratio
-        self._nbits_from  = nbits_from
+        self._nbits_from = nbits_from
         self._reverse = reverse
         self._report_valid_token_count = report_valid_token_count
 
@@ -195,7 +195,8 @@ class _UpConverter(Elaboratable):
                 for i in range(self.ratio):
                     with m.Case(i):
                         n = self.ratio-i-1 if self._reverse else i
-                        m.d.sync += self.source.payload.lower()[n*self._nbits_from:(n+1)*self._nbits_from].eq(self.sink.payload)
+                        m.d.sync += self.source.payload.lower()[n*self._nbits_from:(
+                            n+1)*self._nbits_from].eq(self.sink.payload)
 
         if self._report_valid_token_count:
             with m.If(load_part):
@@ -246,7 +247,8 @@ class _DownConverter(Elaboratable):
             for i in range(self.ratio):
                 with m.Case(i):
                     n = self.ratio-i-1 if self._reverse else i
-                    m.d.comb += self.source.data.eq(self.sink.data[n*self._nbits_to:(n+1)*self._nbits_to])
+                    m.d.comb += self.source.data.eq(
+                        self.sink.data[n*self._nbits_to:(n+1)*self._nbits_to])
 
         if self._report_valid_token_count:
             m.d.comb += self.source.valid_token_count.eq(last)
@@ -299,7 +301,7 @@ class Converter(Elaboratable):
                  report_valid_token_count=False):
         cls, ratio = _get_converter_ratio(nbits_from, nbits_to)
         self.specialized = cls(nbits_from, nbits_to, ratio,
-            reverse, report_valid_token_count)
+                               reverse, report_valid_token_count)
         self.sink = self.specialized.sink
         self.source = self.specialized.source
 
@@ -328,7 +330,7 @@ class StrideConverter(Elaboratable):
 
         nbits_from = len(self.sink.payload.lower())
         nbits_to = len(self.source.payload.lower())
-        
+
         m.submodules += self.converter
 
         # cast sink to converter.sink (user fields --> raw bits)
@@ -343,12 +345,13 @@ class StrideConverter(Elaboratable):
                 j = 0
                 for name, width in self._layout_to.payload_layout:
                     src = getattr(self.sink, name)[i*width:(i+1)*width]
-                    dst = self.converter.sink.data[i*nbits_to+j:i*nbits_to+j+width]
+                    dst = self.converter.sink.data[i *
+                                                   nbits_to+j:i*nbits_to+j+width]
                     m.d.comb += dst.eq(src)
                     j += width
         else:
-            m.d.comb += self.converter.sink.payload.eq(self.sink.payload.lower())
-
+            m.d.comb += self.converter.sink.payload.eq(
+                self.sink.payload.lower())
 
         # cast converter.source to source (raw bits --> user fields)
         m.d.comb += [
@@ -361,7 +364,8 @@ class StrideConverter(Elaboratable):
             for i in range(ratio):
                 j = 0
                 for name, width in self._layout_from.payload_layout:
-                    src = self.converter.source.data[i*nbits_from+j:i*nbits_from+j+width]
+                    src = self.converter.source.data[i *
+                                                     nbits_from+j:i*nbits_from+j+width]
                     dst = getattr(self.source, name)[i*width:(i+1)*width]
                     m.d.comb += dst.eq(src)
                     j += width
@@ -370,6 +374,7 @@ class StrideConverter(Elaboratable):
 
         return m
 
+
 class Pipeline(Elaboratable):
     def __init__(self, *modules):
         self._modules = modules
@@ -389,7 +394,7 @@ class Pipeline(Elaboratable):
 
         n = len(self._modules)
         mod = self._modules[0]
-        
+
         for i in range(1, n):
             mod_n = self._modules[i]
             if isinstance(mod, Endpoint):