From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 1 May 2021 15:24:49 +0000 (+0100)
Subject: add MMUTestCaseROM
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b33f2c9578d2d7f62d35a832041d21d67e9791b;p=soc.git

add MMUTestCaseROM
---

diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py
index 13b278b2..5b995afc 100644
--- a/src/soc/simple/test/test_issuer_mmu.py
+++ b/src/soc/simple/test/test_issuer_mmu.py
@@ -20,6 +20,7 @@ from soc.simple.test.test_runner import TestRunner
 
 # test with MMU
 from openpower.test.mmu.mmu_cases import MMUTestCase
+from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
 #from openpower.test.ldst.ldst_cases import LDSTTestCase
 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
 
@@ -40,6 +41,9 @@ if __name__ == "__main__":
     #                          microwatt_mmu=True))
     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
                               microwatt_mmu=True))
+    suite.addTest(TestRunner(MMUTestCaseROM().test_data, svp64=svp64,
+                              microwatt_mmu=True,
+                              rom=default_mem))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)