From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Tue, 28 Jul 2020 15:47:49 +0000 (+0200)
Subject: Remove classes for read and write ports, add  parameter check to gramNativePort
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b39dffd2047652e2f8a6a32d34350859f0fc763;p=gram.git

Remove classes for read and write ports, add  parameter check to gramNativePort
---

diff --git a/gram/common.py b/gram/common.py
index fe31422..3da6c7d 100644
--- a/gram/common.py
+++ b/gram/common.py
@@ -181,6 +181,9 @@ class gramNativePort(Settings):
     def __init__(self, mode, address_width, data_width, clock_domain="sync", id=0):
         self.set_attributes(locals())
 
+        if mode not in ["both", "read", "write"]:
+            raise ValueError("mode must be either both/read/write, not {!r}".format(mode))
+
         self.lock = Signal()
 
         self.cmd = stream.Endpoint(cmd_description(address_width))
@@ -204,16 +207,6 @@ class gramNativePort(Settings):
             return self.cmd.addr[:cba_shift]
 
 
-class gramNativeWritePort(gramNativePort):
-    def __init__(self, *args, **kwargs):
-        gramNativePort.__init__(self, "write", *args, **kwargs)
-
-
-class gramNativeReadPort(gramNativePort):
-    def __init__(self, *args, **kwargs):
-        gramNativePort.__init__(self, "read", *args, **kwargs)
-
-
 # Timing Controllers -------------------------------------------------------------------------------
 
 class tXXDController(Elaboratable):