From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 19:14:23 +0000 (-0700)
Subject: opt_expr: Sx to Sz; spotted by @Xiretza
X-Git-Tag: working-ls180~552
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b3a4a1fff297481a463f27da250af8436041753;p=yosys.git

opt_expr: Sx to Sz; spotted by @Xiretza
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 63811c1a1..777a24777 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -175,7 +175,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 			}
 		}
 
-		bool def = (bit_a != State::Sx && bit_a != State::Sz && bit_b != State::Sx && bit_b != State::Sx);
+		bool def = (bit_a != State::Sx && bit_a != State::Sz && bit_b != State::Sx && bit_b != State::Sz);
 		if (def || !keepdc) {
 			if (bit_a.wire == NULL && bit_b.wire == NULL)
 				group_idx = GRP_CONST_AB;