From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 23 Aug 2019 10:17:55 +0000 (+0100)
Subject: remove need to pass register_levels to AddReduceSingle
X-Git-Tag: ls180-24jan2020~411
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b4588e1710b0e997b9dd5d1f0376150afe276ce;p=ieee754fpu.git

remove need to pass register_levels to AddReduceSingle
---

diff --git a/src/ieee754/part_mul_add/multiply.py b/src/ieee754/part_mul_add/multiply.py
index 672bbfd3..92afc2bb 100644
--- a/src/ieee754/part_mul_add/multiply.py
+++ b/src/ieee754/part_mul_add/multiply.py
@@ -616,7 +616,7 @@ class AddReduce(Elaboratable):
         m.d.comb += i.eq_from(partition_points, inputs, part_ops)
         for idx in range(len(self.levels)):
             mcur = self.levels[idx]
-            if 0 in mcur.register_levels:
+            if idx in self.register_levels:
                 m.d.sync += mcur.i.eq(i)
             else:
                 m.d.comb += mcur.i.eq(i)