From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 20 Sep 2017 17:47:11 +0000 (-0700)
Subject: Verify that mtval/stval is written correctly on misaligned fetch
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b4922e130bb520f9328dca77cf7330df96ce2f9;p=riscv-tests.git

Verify that mtval/stval is written correctly on misaligned fetch
---

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index d4e5b44..eb50f94 100644
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -17,6 +17,7 @@ RVTEST_CODE_BEGIN
   #define sscratch mscratch
   #define sstatus mstatus
   #define scause mcause
+  #define sbadaddr mbadaddr
   #define sepc mepc
   #define sret mret
   #define stvec_handler mtvec_handler
@@ -132,9 +133,16 @@ stvec_handler:
 
   # verify that epc == &jalr (== t0 - 4)
   csrr a1, sepc
-  addi t0, t0, -4
+  addi a1, a1, 4
   bne t0, a1, fail
 
+  # verify that badaddr == 0 or badaddr == t0+2.
+  csrr a0, sbadaddr
+  beqz a0, 1f
+  addi a0, a0, -2
+  bne a0, t0, fail
+1:
+
   addi a1, a1, 12
   csrw sepc, a1
   sret