From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 17 Apr 2018 06:20:14 +0000 (+0100)
Subject: add vector length pseudocode
X-Git-Tag: convert-csv-opcode-to-binary~5630
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b4d349041541456572ab61e8b38bf2ac48dd0ce;p=libreriscv.git

add vector length pseudocode
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index ad2ced559..98791b007 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1073,6 +1073,7 @@ This is interpreted as follows:
 * Given that the context is RV32, ELEN=32.
 * With ELEN=32 and bitwidth=16, the number of SIMD elements is 2
 * Therefore the actual vector length is up to *six* elements
+* However vsetl sets a length 5 therefore the last "element" is skipped
 
 So when using an operation that uses r2 as a source (or destination)
 the operation is carried out as follows: