From: Tsukasa OI Date: Thu, 11 Aug 2022 21:16:51 +0000 (+0900) Subject: RISC-V: Assign DWARF numbers to vector registers X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b4f240762ffa03e65e17cb7dee807bc1628c24a;p=binutils-gdb.git RISC-V: Assign DWARF numbers to vector registers This commit assigns DWARF register numbers to vector registers (v0-v31: 96..127) to implement RISC-V DWARF Specification version 1.0-rc4 (now in the frozen state): https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4 binutils/ChangeLog: * dwarf.c (dwarf_regnames_riscv): Assign DWARF register numbers 96..127 to vector registers v0-v31. gas/ChangeLog: * config/tc-riscv.c (tc_riscv_regname_to_dw2regnum): Support vector registers. * testsuite/gas/riscv/dw-regnums.s: Add vector registers to the DWARF register number test. * testsuite/gas/riscv/dw-regnums.d: Likewise. --- diff --git a/binutils/dwarf.c b/binutils/dwarf.c index aef0f77eab6..c6340a28906 100644 --- a/binutils/dwarf.c +++ b/binutils/dwarf.c @@ -8540,16 +8540,24 @@ init_dwarf_regnames_s390 (void) static const char *const dwarf_regnames_riscv[] = { - "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", /* 0 - 7 */ - "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", /* 8 - 15 */ - "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", /* 16 - 23 */ - "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", /* 24 - 31 */ - "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", /* 32 - 39 */ - "fs0", "fs1", /* 40 - 41 */ - "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", /* 42 - 49 */ - "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", /* 50 - 57 */ - "fs10", "fs11", /* 58 - 59 */ - "ft8", "ft9", "ft10", "ft11" /* 60 - 63 */ + "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", /* 0 - 7 */ + "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", /* 8 - 15 */ + "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", /* 16 - 23 */ + "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", /* 24 - 31 */ + "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", /* 32 - 39 */ + "fs0", "fs1", /* 40 - 41 */ + "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", /* 42 - 49 */ + "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", /* 50 - 57 */ + "fs10", "fs11", /* 58 - 59 */ + "ft8", "ft9", "ft10", "ft11", /* 60 - 63 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 64 - 71 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 72 - 79 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 80 - 87 */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 88 - 95 */ + "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", /* 96 - 103 */ + "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", /* 104 - 111 */ + "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", /* 112 - 119 */ + "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", /* 120 - 127 */ }; /* A RISC-V replacement for REGNAME_INTERNAL_BY_TABLE_ONLY which handles diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index bd8f65d94fd..f64b446bf11 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -4406,6 +4406,9 @@ tc_riscv_regname_to_dw2regnum (char *regname) if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) return reg + 32; + if ((reg = reg_lookup_internal (regname, RCLASS_VECR)) >= 0) + return reg + 96; + /* CSRs are numbered 4096 -> 8191. */ if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0) return reg + 4096; diff --git a/gas/testsuite/gas/riscv/dw-regnums.d b/gas/testsuite/gas/riscv/dw-regnums.d index 5f1c879a7ac..5ec61b98697 100644 --- a/gas/testsuite/gas/riscv/dw-regnums.d +++ b/gas/testsuite/gas/riscv/dw-regnums.d @@ -1,4 +1,4 @@ -#as: -march=rv32if +#as: -march=rv32iv #objdump: --dwarf=frames @@ -145,4 +145,36 @@ Contents of the .* section: DW_CFA_offset_extended_sf: r61 \(ft9\) at cfa\+248 DW_CFA_offset_extended_sf: r62 \(ft10\) at cfa\+252 DW_CFA_offset_extended_sf: r63 \(ft11\) at cfa\+256 + DW_CFA_offset_extended_sf: r96 \(v0\) at cfa\+388 + DW_CFA_offset_extended_sf: r97 \(v1\) at cfa\+392 + DW_CFA_offset_extended_sf: r98 \(v2\) at cfa\+396 + DW_CFA_offset_extended_sf: r99 \(v3\) at cfa\+400 + DW_CFA_offset_extended_sf: r100 \(v4\) at cfa\+404 + DW_CFA_offset_extended_sf: r101 \(v5\) at cfa\+408 + DW_CFA_offset_extended_sf: r102 \(v6\) at cfa\+412 + DW_CFA_offset_extended_sf: r103 \(v7\) at cfa\+416 + DW_CFA_offset_extended_sf: r104 \(v8\) at cfa\+420 + DW_CFA_offset_extended_sf: r105 \(v9\) at cfa\+424 + DW_CFA_offset_extended_sf: r106 \(v10\) at cfa\+428 + DW_CFA_offset_extended_sf: r107 \(v11\) at cfa\+432 + DW_CFA_offset_extended_sf: r108 \(v12\) at cfa\+436 + DW_CFA_offset_extended_sf: r109 \(v13\) at cfa\+440 + DW_CFA_offset_extended_sf: r110 \(v14\) at cfa\+444 + DW_CFA_offset_extended_sf: r111 \(v15\) at cfa\+448 + DW_CFA_offset_extended_sf: r112 \(v16\) at cfa\+452 + DW_CFA_offset_extended_sf: r113 \(v17\) at cfa\+456 + DW_CFA_offset_extended_sf: r114 \(v18\) at cfa\+460 + DW_CFA_offset_extended_sf: r115 \(v19\) at cfa\+464 + DW_CFA_offset_extended_sf: r116 \(v20\) at cfa\+468 + DW_CFA_offset_extended_sf: r117 \(v21\) at cfa\+472 + DW_CFA_offset_extended_sf: r118 \(v22\) at cfa\+476 + DW_CFA_offset_extended_sf: r119 \(v23\) at cfa\+480 + DW_CFA_offset_extended_sf: r120 \(v24\) at cfa\+484 + DW_CFA_offset_extended_sf: r121 \(v25\) at cfa\+488 + DW_CFA_offset_extended_sf: r122 \(v26\) at cfa\+492 + DW_CFA_offset_extended_sf: r123 \(v27\) at cfa\+496 + DW_CFA_offset_extended_sf: r124 \(v28\) at cfa\+500 + DW_CFA_offset_extended_sf: r125 \(v29\) at cfa\+504 + DW_CFA_offset_extended_sf: r126 \(v30\) at cfa\+508 + DW_CFA_offset_extended_sf: r127 \(v31\) at cfa\+512 #... diff --git a/gas/testsuite/gas/riscv/dw-regnums.s b/gas/testsuite/gas/riscv/dw-regnums.s index 6686e8b9385..bbe1b13d894 100644 --- a/gas/testsuite/gas/riscv/dw-regnums.s +++ b/gas/testsuite/gas/riscv/dw-regnums.s @@ -1,6 +1,8 @@ # Check that CFI directives can accept all of the register names (including # aliases). The results for this test also ensures that the DWARF -# register numbers for the GPRs/FPRs registers shouldn't change. +# register numbers for the GPRs/FPRs/vector registers shouldn't change. +# Note that, because vector register size is "variable" in principle, +# vector registers are very unlikely to be used within .cfi_offset directive. .text .global _start @@ -144,5 +146,39 @@ _start: .cfi_offset f30, 252 .cfi_offset f31, 256 + # Vector registers (numeric only) + .cfi_offset v0, 388 + .cfi_offset v1, 392 + .cfi_offset v2, 396 + .cfi_offset v3, 400 + .cfi_offset v4, 404 + .cfi_offset v5, 408 + .cfi_offset v6, 412 + .cfi_offset v7, 416 + .cfi_offset v8, 420 + .cfi_offset v9, 424 + .cfi_offset v10, 428 + .cfi_offset v11, 432 + .cfi_offset v12, 436 + .cfi_offset v13, 440 + .cfi_offset v14, 444 + .cfi_offset v15, 448 + .cfi_offset v16, 452 + .cfi_offset v17, 456 + .cfi_offset v18, 460 + .cfi_offset v19, 464 + .cfi_offset v20, 468 + .cfi_offset v21, 472 + .cfi_offset v22, 476 + .cfi_offset v23, 480 + .cfi_offset v24, 484 + .cfi_offset v25, 488 + .cfi_offset v26, 492 + .cfi_offset v27, 496 + .cfi_offset v28, 500 + .cfi_offset v29, 504 + .cfi_offset v30, 508 + .cfi_offset v31, 512 + nop .cfi_endproc