From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Wed, 1 Jul 2020 16:57:52 +0000 (+0200)
Subject: Fix Iverilog simulation
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b509938d7fbffb96de8223f3e676d75a70d0d5f;p=gram.git

Fix Iverilog simulation
---

diff --git a/gram/simulation/icarusecpix5platform.py b/gram/simulation/icarusecpix5platform.py
index 8185e7f..1f0c9c6 100644
--- a/gram/simulation/icarusecpix5platform.py
+++ b/gram/simulation/icarusecpix5platform.py
@@ -165,14 +165,6 @@ class IcarusECPIX5Platform(LatticeECP5Platform):
     def file_templates(self):
         return {
             **TemplatedPlatform.build_script_templates,
-            "{{name}}.v": r"""
-            /* {{autogenerated}} */
-            {{emit_verilog()}}
-            """,
-            "{{name}}.debug.v": r"""
-            /* {{autogenerated}} */
-            {{emit_debug_verilog()}}
-            """,
             "{{name}}.il": r"""
             # {{autogenerated}}
             {{emit_rtlil()}}
diff --git a/gram/simulation/runsimsoc.sh b/gram/simulation/runsimsoc.sh
index 9321c40..5f71fa4 100755
--- a/gram/simulation/runsimsoc.sh
+++ b/gram/simulation/runsimsoc.sh
@@ -4,7 +4,8 @@ set -e
 LIB_DIR=/usr/local/diamond/3.11_x64/ispfpga/verilog/data/ecp5u
 
 python simsoc.py
-iverilog -Wall -g2012 -s simsoctb -o simsoc simsoctb.v build_simsoc/top.debug.v dram_model/ddr3.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
+yosys simsoc.ys
+iverilog -Wall -g2012 -s simsoctb -o simsoc simsoctb.v build_simsoc/top.v dram_model/ddr3.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
 	${LIB_DIR}/FD1S3AX.v ${LIB_DIR}/SGSR.v ${LIB_DIR}/ODDRX2F.v ${LIB_DIR}/ODDRX2DQA.v ${LIB_DIR}/DELAYF.v ${LIB_DIR}/BB.v ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v \
 	${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v DDRDLLA.patched.v \
 	${LIB_DIR}/CLKDIVF.v
diff --git a/gram/simulation/simcrgtb.v b/gram/simulation/simcrgtb.v
index 372a5e2..6814343 100644
--- a/gram/simulation/simcrgtb.v
+++ b/gram/simulation/simcrgtb.v
@@ -1,6 +1,6 @@
 // This file is Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
 
-`timescale 1 ns / 10 fs
+`timescale 1 ns / 1 ns
 
 module top;
   // GSR & PUR init requires for Lattice models
diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index 19d57bd..8f50714 100644
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -152,80 +152,17 @@ class ECPIX5CRG(Elaboratable):
 
         return m
 
-class OldCRG(Elaboratable):
-    def elaborate(self, platform):
-        m = Module()
-
-        m.submodules.pll = pll = PLL(ClockSignal(
-            "sync"), CLKI_DIV=1, CLKFB_DIV=2, CLK1_DIV=2, CLK2_DIV=16)
-        cd_sync2x = ClockDomain("sync2x", local=False)
-        m.d.comb += cd_sync2x.clk.eq(pll.clkout1)
-        m.domains += cd_sync2x
-
-        cd_init = ClockDomain("init", local=False)
-        m.d.comb += cd_init.clk.eq(pll.clkout2)
-        m.domains += cd_init
-
-        return m
-
-class ThinCRG(Elaboratable):
-    """
-    Sync (clk100, resetless) => PLL => sync2x_unbuf (200Mhz) => ECLKSYNC => sync2x => CLKDIVF => dramsync
-    """
-
-    def __init__(self):
-        ...
-
-    def elaborate(self, platform):
-        m = Module()
-
-        # Power-on delay (655us)
-        podcnt = Signal(16, reset=2**16-1)
-        pod_done = Signal()
-        with m.If(podcnt != 0):
-            m.d.sync += podcnt.eq(podcnt-1)
-        m.d.comb += pod_done.eq(podcnt == 0)
-
-        # Generating sync2x (200Mhz) and init (25Mhz) from clk100
-        cd_sync2x = ClockDomain("sync2x", local=False)
-        cd_sync2x_unbuf = ClockDomain("sync2x_unbuf", local=True, reset_less=True)
-        cd_init = ClockDomain("init", local=False)
-        cd_dramsync = ClockDomain("dramsync", local=False)
-        m.submodules.pll = pll = PLL(ClockSignal("sync"), CLKI_DIV=1, CLKFB_DIV=2, CLK1_DIV=2, CLK2_DIV=16, CLK3_DIV=4,
-            clkout1=ClockSignal("sync2x_unbuf"), clkout2=ClockSignal("init"))
-        m.submodules += Instance("ECLKSYNCB",
-                i_ECLKI = ClockSignal("sync2x_unbuf"),
-                i_STOP  = 0,
-                o_ECLKO = ClockSignal("sync2x"))
-        m.domains += cd_sync2x_unbuf
-        m.domains += cd_sync2x
-        m.domains += cd_init
-        m.domains += cd_dramsync
-        m.d.comb += ResetSignal("init").eq(~pll.lock|~pod_done)
-        m.d.comb += ResetSignal("dramsync").eq(~pll.lock|~pod_done)
-
-        # Generating sync (100Mhz) from sync2x
-        m.submodules += Instance("CLKDIVF",
-            p_DIV="2.0",
-            i_ALIGNWD=0,
-            i_CLKI=ClockSignal("sync2x"),
-            i_RST=0,
-            o_CDIVX=ClockSignal("dramsync"))
-
-        return m
-
-
 class DDR3SoC(SoC, Elaboratable):
     def __init__(self, *, clk_freq,
                  ddrphy_addr, dramcore_addr,
                  ddr_addr):
+        self.crg = ECPIX5CRG()
+
         self._arbiter = wishbone.Arbiter(addr_width=30, data_width=32, granularity=8,
                                          features={"cti", "bte"})
         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
                                          features={"cti", "bte"})
 
-        self.crg = ECPIX5CRG()
-
         self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))
         self._arbiter.add(self.ub.bus)
 
diff --git a/gram/simulation/simsoc.ys b/gram/simulation/simsoc.ys
new file mode 100644
index 0000000..35e11ea
--- /dev/null
+++ b/gram/simulation/simsoc.ys
@@ -0,0 +1,16 @@
+read_ilang build_simsoc/top.il
+delete w:$verilog_initial_trigger
+proc_prune
+proc_clean
+proc_init
+proc_arst
+proc_dff
+proc_rmdead
+proc_mux
+proc_clean
+pmuxtree
+memory_collect
+extract_fa -v
+clean
+opt -fine -full
+write_verilog -norename build_simsoc/top.v