From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 13 Dec 2023 00:51:33 +0000 (-0800)
Subject: caller.py: use yield from on is_ffirst_mode since it's a generator
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b59ce4bd85670d0044cfe11d840bc2b9dba69cb;p=openpower-isa.git

caller.py: use yield from on is_ffirst_mode since it's a generator
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index b0b09f06..8bbd7bb1 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -2441,7 +2441,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         log("        vli", vli_)
         log("     cr_bit", cr_bit)
         log("      rc_en", rc_en)
-        if not rc_en or not is_ffirst_mode(self.dec2):
+        ffirst = yield from is_ffirst_mode(self.dec2)
+        if not rc_en or not ffirst:
             return False, False
         # get the CR vevtor, do BO-test
         crf = "CR0"
@@ -2983,7 +2984,8 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
         # allowing *scalar destinations* to be used as an accumulator.
         # effectively this implies /mr (mapreduce mode) is 100% on with ddffirst
         # see https://bugs.libre-soc.org/show_bug.cgi?id=1183#c16
-        if is_ffirst_mode(self.dec2):
+        ffirst = yield from is_ffirst_mode(self.dec2)
+        if ffirst:
             svp64_is_vector = in_vec
 
         # loops end at the first "hit" (source or dest)