From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 8 Dec 2014 09:56:43 +0000 (+0100)
Subject: Added more documentation fixmes for nontrivial register cells
X-Git-Tag: yosys-0.5~262
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b62bbeee824f1ff6d483247f5613e597b8c854f;p=yosys.git

Added more documentation fixmes for nontrivial register cells
---

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 64d3633e9..c12d8734e 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -357,7 +357,7 @@ Add a brief description of the {\tt \$fsm} cell type.
 For gate level logic networks, fixed function single bit cells are used that do
 not provide any parameters.
 
-Simulation models for these cells can be found in the file {\tt techlibs/common/stdcells\_sim.v} in the Yosys
+Simulation models for these cells can be found in the file {\tt techlibs/common/simcells.v} in the Yosys
 source tree.
 
 \begin{table}[t]
@@ -428,6 +428,14 @@ Add information about {\tt \$slice} and {\tt \$concat} cells.
 Add information about {\tt \$alu}, {\tt \$macc}, {\tt \$fa}, and {\tt \$lcu} cells.
 \end{fixme}
 
+\begin{fixme}
+Add information about {\tt \$dffe}, {\tt \$dffsr}, {\tt \$dlatch}, and {\tt \$dlatchsr} cells.
+\end{fixme}
+
+\begin{fixme}
+Add information about {\tt \$\_DFFE\_??\_}, {\tt \$\_DFFSR\_???\_}, {\tt \$\_DLATCH\_?\_}, and {\tt \$\_DLATCHSR\_???\_} cells.
+\end{fixme}
+
 \begin{fixme}
 Add information about {\tt \$\_NAND\_}, {\tt \$\_NOR\_}, {\tt \$\_XNOR\_}, {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells.
 \end{fixme}