From: lkcl <lkcl@web>
Date: Sat, 28 Aug 2021 18:02:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~284
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b805e81461e52467e48413f6d112cb703c41b2f;p=libreriscv.git

---

diff --git a/openpower/sv/av_opcodes.mdwn b/openpower/sv/av_opcodes.mdwn
index a51acdb5c..470bcf1f1 100644
--- a/openpower/sv/av_opcodes.mdwn
+++ b/openpower/sv/av_opcodes.mdwn
@@ -98,7 +98,19 @@ signed and unsigned, 8/16/32: these are all of the form:
     result = (src1 > src2) ? src1 : src2 # max
     result = (src1 < src2) ? src1 : src2 # min
 
-*These do not exist in the scalar INTEGER ISA and would need to be added*
+*These do not exist in the scalar INTEGER ISA and would need to be added*.
+There are additionally no scalar FP min/max, either. These also
+need to be added.
+
+Also it makes sense for both the integer and FP variants
+to have Rc=1 modes, where those modes are based on the
+respective cmp (or fsel / isel) behaviour. In other words,
+the Rc=1 setting is based on the *comparison* of the
+two inputs, rather than on which of the two results was
+returned by the min/max opcode.
+
+    result = (src1 > src2) ? src1 : src2 # max
+    CR0 = CR_computr(src2-src1) # not based on result
 
 ## vmerge operations