From: Luke Kenneth Casson Leighton Date: Fri, 31 Dec 2021 16:09:35 +0000 (+0000) Subject: mention MyHDL for compare/contrast to nmigen X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7b9e6e42b8bfa6ccfdffd0e8ee83e564fc399281;p=nmigen.git mention MyHDL for compare/contrast to nmigen --- diff --git a/README.md b/README.md index 1195b25..401983a 100644 --- a/README.md +++ b/README.md @@ -54,10 +54,12 @@ The development of nMigen has been supported by [M-Labs][] and nMigen is *not* a "Python-to-FPGA" conventional high level synthesis (HLS) tool. It will *not* take a Python program as input and generate a -hardware implementation of it. In nMigen, the Python program is executed -by a regular Python interpreter, and it emits explicit statements in the -FHDL domain-specific language. Writing a conventional HLS tool that uses -nMigen as an internal component might be a good idea, on the other hand :) +hardware implementation of it. If you prefer this style of HLS, you may +wish to try [MyHDL](https://myhdl.org). In nMigen, the Python program is +executed by a regular Python interpreter, and it emits explicit statements +in the FHDL domain-specific language. Writing a conventional HLS tool, +similar to MyHDL, that uses nMigen as an internal component might be a +good idea, on the other hand :) ### Installation