From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 29 May 2019 20:35:37 +0000 (+0100)
Subject: allow SRLatch to be multibit
X-Git-Tag: ls180-24jan2020~996
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ba19cf0b3212f0bbfa9bc1a88174027406e1e87;p=ieee754fpu.git

allow SRLatch to be multibit
---

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index cf41a0d3..460661ba 100644
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -1,6 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
-from nmigen import Signal, Module, Elaboratable
+from nmigen import Signal, Module, Const, Elaboratable
 
 """ jk latch
 
@@ -31,17 +31,18 @@ def latchregister(m, incoming, outgoing, settrue):
 
 
 class SRLatch(Elaboratable):
-    def __init__(self, sync=True):
+    def __init__(self, sync=True, llen=1):
         self.sync = sync
-        self.s = Signal(reset=0)
-        self.r = Signal(reset=1) # defaults to off
-        self.q = Signal(reset_less=True)
-        self.qn = Signal(reset_less=True)
-        self.qlq = Signal(reset_less=True)
+        self.llen = llen
+        self.s = Signal(llen, reset=0)
+        self.r = Signal(llen, reset=(1<<llen)-1) # defaults to off
+        self.q = Signal(llen, reset_less=True)
+        self.qn = Signal(llen, reset_less=True)
+        self.qlq = Signal(llen, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
-        q_int = Signal()
+        q_int = Signal(self.llen)
 
         m.d.sync += q_int.eq((q_int & ~self.r) | self.s)
         if self.sync: