From: Tobias Platen <tplaten@posteo.de>
Date: Thu, 28 May 2020 12:22:45 +0000 (+0200)
Subject: fixes for l0_cache.py
X-Git-Tag: div_pipeline~770
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ba6bd27618ba619814fc669ebc76fbf55cce966;p=soc.git

fixes for l0_cache.py
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index e9fdfcd8..6a1cefc7 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -195,17 +195,19 @@ class DataMerger(Elaboratable):
             comb, sync = m.d.comb, m.d.sync
             #(1) pick a row
             m.submodules.pick = pick = PriorityEncoder(self.array_size)
-            pick.i.eq(0)
-            for j in range(self.addr):
-                with m.If(self.addr_match_i[j]>0):
+            for j in range(self.array_size):
+                with m.If(self.addr_match_i[j].bool()):
                     pick.i.eq(pick.i||(1<<j))
             valid = ~pick.n
             idx = pick.o
             #(2) merge
-            self.data_o.eq(0)
+            #not needed # self.data_o.eq(0)
+            #TODO
+            l = []
             for j in range(self.array_size):
-                with m.If(self.addr_match_i[idx][j] && valid):
-                    self.data_o.eq(self.data_i[j]|self.data_o)
+                select = self.addr_match_i[idx][j] & valid
+                l.append(Mux(select, self.data_i[j], 0))
+            self.data_o.eq(ortreereduce(l))
 
 
 class LDSTPort(Elaboratable):