From: lkcl Date: Fri, 21 Apr 2023 00:15:47 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7baecfb3bf7c9fc39a8135ef73d62137413a98a9;p=libreriscv.git --- diff --git a/openpower/sv/po9_encoding.mdwn b/openpower/sv/po9_encoding.mdwn index 51d64c546..500ad33ab 100644 --- a/openpower/sv/po9_encoding.mdwn +++ b/openpower/sv/po9_encoding.mdwn @@ -123,11 +123,15 @@ Encoding spaces and their potential are illustrated: Notes: -* Prefixed-Prefixed (96-bit) instructions are prohibited. EXT1xx is +* PO9-PO1 Prefixed-Prefixed (96-bit) instructions are prohibited. EXT1xx is thus inherently UnVectoriseable as the EXT1xx prefix is 32-bit on top of an SVP64 prefix which is 32-bit on top of a Defined Word and the complexity at the Decoder becomes too great for High Performance Multi-Issue systems. +* PO1-PO9 Prefixed-Prefixed (96-bit) instructions are also prohibited + for the same reason: Multi-Issue Decode complexity is too great. +* There is however no reason why PO1-PO9 (EXT109) as a 64-bit Encoding + should not be permitted as long as it is clearly marked as UnVectoriseable. * EXT100-163 instructions (PO1-Prefixed) are also prohibited from being double-PO1-prefixed (not twice prefixed) * RESERVED2 presently remains unallocated as of yet and therefore its