From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 28 Jul 2014 09:08:55 +0000 (+0200)
Subject: Using log_assert() instead of assert()
X-Git-Tag: yosys-0.4~379
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7bd2d1064f2eceddc3c93c121c4154a2f594a040;p=yosys.git

Using log_assert() instead of assert()
---

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 2b783e734..d167c3f4e 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -27,7 +27,6 @@
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 
 struct BlifDumperConfig
 {
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 4af121005..f721fdc99 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -549,7 +549,7 @@ struct BtorDumper
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				l1_width = pow(2, ceil(log(l1_width)/log(2)));
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
-				//assert(l2_width <= ceil(log(l1_width)/log(2)) );
+				//log_assert(l2_width <= ceil(log(l1_width)/log(2)) );
 				int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
 				int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 5eff4598a..49f719a4a 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -26,7 +26,6 @@
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 
 #define EDIF_DEF(_id) edif_names(RTLIL::unescape_id(_id), true).c_str()
 #define EDIF_REF(_id) edif_names(RTLIL::unescape_id(_id), false).c_str()
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index d45e94a09..87a3d6cb3 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -27,7 +27,6 @@
 #include "kernel/register.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 #include <string.h>
 #include <errno.h>
 
@@ -41,7 +40,7 @@ void ILANG_BACKEND::dump_const(FILE *f, const RTLIL::Const &data, int width, int
 		if (width == 32 && autoint) {
 			int32_t val = 0;
 			for (int i = 0; i < width; i++) {
-				assert(offset+i < (int)data.bits.size());
+				log_assert(offset+i < (int)data.bits.size());
 				switch (data.bits[offset+i]) {
 				case RTLIL::S0: break;
 				case RTLIL::S1: val |= 1 << i; break;
@@ -55,7 +54,7 @@ void ILANG_BACKEND::dump_const(FILE *f, const RTLIL::Const &data, int width, int
 		}
 		fprintf(f, "%d'", width);
 		for (int i = offset+width-1; i >= offset; i--) {
-			assert(i < (int)data.bits.size());
+			log_assert(i < (int)data.bits.size());
 			switch (data.bits[i]) {
 			case RTLIL::S0: fprintf(f, "0"); break;
 			case RTLIL::S1: fprintf(f, "1"); break;
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 2f94e290d..9faed77c9 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -23,7 +23,6 @@
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 
 
 static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 283448c3b..ab5316ec3 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -23,7 +23,6 @@
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
 #include <string>
-#include <assert.h>
 
 static void print_spice_net(FILE *f, RTLIL::SigBit s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
 {
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index f7f0ecaf4..fe2c2b247 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -30,7 +30,6 @@
 #include "kernel/register.h"
 #include "kernel/celltypes.h"
 #include "kernel/log.h"
-#include <assert.h>
 #include <string>
 #include <sstream>
 #include <set>
@@ -161,7 +160,7 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset =
 		if (width == 32 && !no_decimal) {
 			int32_t val = 0;
 			for (int i = offset+width-1; i >= offset; i--) {
-				assert(i < (int)data.bits.size());
+				log_assert(i < (int)data.bits.size());
 				if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
 					goto dump_bits;
 				if (data.bits[i] == RTLIL::S1)
@@ -175,7 +174,7 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset =
 			if (width == 0)
 				fprintf(f, "0");
 			for (int i = offset+width-1; i >= offset; i--) {
-				assert(i < (int)data.bits.size());
+				log_assert(i < (int)data.bits.size());
 				switch (data.bits[i]) {
 				case RTLIL::S0: fprintf(f, "0"); break;
 				case RTLIL::S1: fprintf(f, "1"); break;
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index d38cb5e3f..cec199b63 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -820,7 +820,7 @@ RTLIL::Const AstNode::realAsConst(int width)
 // create a new AstModule from an AST_MODULE AST node
 static AstModule* process_module(AstNode *ast, bool defer)
 {
-	assert(ast->type == AST_MODULE);
+	log_assert(ast->type == AST_MODULE);
 
 	if (defer)
 		log("Storing AST representation for module `%s'.\n", ast->str.c_str());
@@ -925,7 +925,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 	flag_icells = icells;
 	flag_autowire = autowire;
 
-	assert(current_ast->type == AST_DESIGN);
+	log_assert(current_ast->type == AST_DESIGN);
 	for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
 		if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
 			(*it)->str = (*it)->str.substr(1);
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 95e15903b..25881d639 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -32,7 +32,6 @@
 
 #include <sstream>
 #include <stdarg.h>
-#include <assert.h>
 #include <algorithm>
 
 using namespace AST;
@@ -137,7 +136,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
 // helper function for creating RTLIL code for multiplexers
 static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
 {
-	assert(cond.size() == 1);
+	log_assert(cond.size() == 1);
 
 	std::stringstream sstr;
 	sstr << "$ternary$" << that->filename << ":" << that->linenum << "$" << (RTLIL::autoidx++);
@@ -267,7 +266,7 @@ struct AST_INTERNAL::ProcessGenerator
 			sync->type = RTLIL::SyncType::STi;
 			proc->syncs.push_back(sync);
 
-			assert(init_lvalue.size() == init_rvalue.size());
+			log_assert(init_lvalue.size() == init_rvalue.size());
 
 			int offset = 0;
 			for (auto &init_lvalue_c : init_lvalue.chunks()) {
@@ -316,7 +315,7 @@ struct AST_INTERNAL::ProcessGenerator
 		case AST_CASE:
 			for (auto child : ast->children)
 				if (child != ast->children[0]) {
-					assert(child->type == AST_COND);
+					log_assert(child->type == AST_COND);
 					collect_lvalues(reg, child, type_eq, type_le, false);
 				}
 			break;
@@ -341,7 +340,7 @@ struct AST_INTERNAL::ProcessGenerator
 			break;
 
 		default:
-			assert(0);
+			log_abort();
 		}
 
 		if (run_sort_and_unify)
@@ -371,7 +370,7 @@ struct AST_INTERNAL::ProcessGenerator
 			init_rvalue.append(lvalue.extract(initSyncSignals, &rvalue));
 			lvalue.remove2(initSyncSignals, &rvalue);
 		}
-		assert(lvalue.size() == rvalue.size());
+		log_assert(lvalue.size() == rvalue.size());
 
 		int offset = 0;
 		for (auto &lvalue_c : lvalue.chunks()) {
@@ -445,7 +444,7 @@ struct AST_INTERNAL::ProcessGenerator
 				{
 					if (child == ast->children[0])
 						continue;
-					assert(child->type == AST_COND);
+					log_assert(child->type == AST_COND);
 
 					subst_lvalue_from = backup_subst_lvalue_from;
 					subst_lvalue_to = backup_subst_lvalue_to;
@@ -815,9 +814,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				log_error("Re-definition of memory `%s' at %s:%d!\n",
 						str.c_str(), filename.c_str(), linenum);
 
-			assert(children.size() >= 2);
-			assert(children[0]->type == AST_RANGE);
-			assert(children[1]->type == AST_RANGE);
+			log_assert(children.size() >= 2);
+			log_assert(children[0]->type == AST_RANGE);
+			log_assert(children[1]->type == AST_RANGE);
 
 			if (!children[0]->range_valid || !children[1]->range_valid)
 				log_error("Memory `%s' with non-constant width or size at %s:%d!\n",
@@ -902,7 +901,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 		use_const_chunk:
 			if (children.size() != 0) {
-				assert(children[0]->type == AST_RANGE);
+				log_assert(children[0]->type == AST_RANGE);
 				if (!children[0]->range_valid) {
 					AstNode *left_at_zero_ast = children[0]->children[0]->clone();
 					AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
@@ -1300,7 +1299,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					}
 					continue;
 				}
-				assert(0);
+				log_abort();
 			}
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 6302260a5..2a55adeff 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -57,7 +57,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 	if (stage == 0)
 	{
-		assert(type == AST_MODULE);
+		log_assert(type == AST_MODULE);
 
 		while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { }
 
@@ -73,7 +73,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			{
 				AstNode *mem = it.first;
 				uint32_t memflags = it.second;
-				assert((memflags & ~0x00ffff00) == 0);
+				log_assert((memflags & ~0x00ffff00) == 0);
 
 				if (mem->get_bool_attribute("\\nomem2reg"))
 					continue;
@@ -480,7 +480,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			// dumpAst(NULL, ">   ");
 			log_error("Index in generate block prefix syntax at %s:%d is not constant!\n", filename.c_str(), linenum);
 		}
-		assert(children[1]->type == AST_IDENTIFIER);
+		log_assert(children[1]->type == AST_IDENTIFIER);
 		newNode = children[1]->clone();
 		const char *second_part = children[1]->str.c_str();
 		if (second_part[0] == '\\')
@@ -506,7 +506,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		range_valid = false;
 		range_left = -1;
 		range_right = 0;
-		assert(children.size() >= 1);
+		log_assert(children.size() >= 1);
 		if (children[0]->type == AST_CONSTANT) {
 			range_valid = true;
 			range_left = children[0]->integer;
@@ -963,8 +963,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 		std::vector<AstNode*> children_list;
 		for (auto child : children) {
-			assert(child->type == AST_ARGUMENT);
-			assert(child->children.size() == 1);
+			log_assert(child->type == AST_ARGUMENT);
+			log_assert(child->children.size() == 1);
 			children_list.push_back(child->children[0]);
 			child->children.clear();
 			delete child;
@@ -1019,7 +1019,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 				op_type = AST_POS;
 			if (str == "not")
 				op_type = AST_POS, invert_results = true;
-			assert(op_type != AST_NONE);
+			log_assert(op_type != AST_NONE);
 
 			AstNode *node = children_list[1];
 			if (op_type != AST_POS)
@@ -1423,13 +1423,13 @@ skip_dynamic_range_lvalue_expansion:;
 
 		if (current_block == NULL)
 		{
-			assert(type == AST_FCALL);
+			log_assert(type == AST_FCALL);
 
 			AstNode *wire = NULL;
 			for (auto child : decl->children)
 				if (child->type == AST_WIRE && child->str == str)
 					wire = child->clone();
-			assert(wire != NULL);
+			log_assert(wire != NULL);
 
 			wire->str = prefix + str;
 			wire->port_id = 0;
@@ -1714,7 +1714,7 @@ skip_dynamic_range_lvalue_expansion:;
 				} else if (children[1]->type == AST_CONSTANT && children[2]->type == AST_CONSTANT) {
 					RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint);
 					RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint);
-					assert(a.bits.size() == b.bits.size());
+					log_assert(a.bits.size() == b.bits.size());
 					for (size_t i = 0; i < a.bits.size(); i++)
 						if (a.bits[i] != b.bits[i])
 							a.bits[i] = RTLIL::State::Sx;
@@ -1761,7 +1761,7 @@ apply_newNode:
 		// fprintf(stderr, "----\n");
 		// dumpAst(stderr, "- ");
 		// newNode->dumpAst(stderr, "+ ");
-		assert(newNode != NULL);
+		log_assert(newNode != NULL);
 		newNode->filename = filename;
 		newNode->linenum = linenum;
 		newNode->cloneInto(this);
@@ -1937,7 +1937,7 @@ void AstNode::mem2reg_as_needed_pass1(std::map<AstNode*, std::set<std::string>>
 
 	uint32_t backup_flags = flags;
 	flags |= children_flags;
-	assert((flags & ~0x000000ff) == 0);
+	log_assert((flags & ~0x000000ff) == 0);
 
 	for (auto child : children)
 		if (ignore_children_counter > 0)
@@ -1986,11 +1986,11 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
 		mod->children.push_back(wire_data);
 		while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
 
-		assert(block != NULL);
+		log_assert(block != NULL);
 		size_t assign_idx = 0;
 		while (assign_idx < block->children.size() && block->children[assign_idx] != this)
 			assign_idx++;
-		assert(assign_idx < block->children.size());
+		log_assert(assign_idx < block->children.size());
 
 		AstNode *assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone());
 		assign_addr->children[0]->str = id_addr;
@@ -2091,7 +2091,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
 				size_t assign_idx = 0;
 				while (assign_idx < block->children.size() && !block->children[assign_idx]->contains(this))
 					assign_idx++;
-				assert(assign_idx < block->children.size());
+				log_assert(assign_idx < block->children.size());
 				block->children.insert(block->children.begin()+assign_idx, case_node);
 				block->children.insert(block->children.begin()+assign_idx, assign_addr);
 			}
@@ -2113,7 +2113,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
 			children.push_back(bit_part_sel);
 	}
 
-	assert(id2ast == NULL || mem2reg_set.count(id2ast) == 0);
+	log_assert(id2ast == NULL || mem2reg_set.count(id2ast) == 0);
 
 	auto children_list = children;
 	for (size_t i = 0; i < children_list.size(); i++)
@@ -2123,7 +2123,7 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
 // calulate memory dimensions
 void AstNode::meminfo(int &mem_width, int &mem_size, int &addr_bits)
 {
-	assert(type == AST_MEMORY);
+	log_assert(type == AST_MEMORY);
 
 	mem_width = children[0]->range_left - children[0]->range_right + 1;
 	mem_size = children[1]->range_left - children[1]->range_right;
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index aee38703b..80170394e 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -22,7 +22,6 @@
 #include "kernel/log.h"
 #include <unistd.h>
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 #include <dirent.h>
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 8491a6b47..446f5e50c 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -36,7 +36,6 @@
 
 #include "verilog_frontend.h"
 #include "kernel/log.h"
-#include <assert.h>
 #include <string.h>
 #include <math.h>
 
@@ -47,7 +46,7 @@ static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
 {
 	int carry = 0;
 	for (size_t i = 0; i < digits.size(); i++) {
-		assert(digits[i] < 10);
+		log_assert(digits[i] < 10);
 		digits[i] += carry * 10;
 		carry = digits[i] % 2;
 		digits[i] /= 2;
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 873ae3d51..67b2ffa7c 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -37,7 +37,6 @@
 #include <stdarg.h>
 #include <stdio.h>
 #include <string.h>
-#include <assert.h>
 
 static std::list<std::string> output_code;
 static std::list<std::string> input_buffer;
@@ -65,7 +64,7 @@ static char next_char()
 	if (input_buffer.empty())
 		return 0;
 
-	assert(input_buffer_charp <= input_buffer.front().size());
+	log_assert(input_buffer_charp <= input_buffer.front().size());
 	if (input_buffer_charp == input_buffer.front().size()) {
 		input_buffer_charp = 0;
 		input_buffer.pop_front();
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 437fc3ec0..cbc594e86 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -33,7 +33,6 @@
 #include "libs/sha1/sha1.h"
 #include <sstream>
 #include <stdarg.h>
-#include <assert.h>
 
 using namespace VERILOG_FRONTEND;
 
diff --git a/frontends/vhdl2verilog/vhdl2verilog.cc b/frontends/vhdl2verilog/vhdl2verilog.cc
index 4392ed444..63dc85acc 100644
--- a/frontends/vhdl2verilog/vhdl2verilog.cc
+++ b/frontends/vhdl2verilog/vhdl2verilog.cc
@@ -22,7 +22,6 @@
 #include "kernel/log.h"
 #include <unistd.h>
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 #include <dirent.h>
diff --git a/kernel/bitpattern.h b/kernel/bitpattern.h
index 05b2bbc24..91f54593f 100644
--- a/kernel/bitpattern.h
+++ b/kernel/bitpattern.h
@@ -66,8 +66,8 @@ struct BitPatternPool
 
 	bool match(bits_t a, bits_t b)
 	{
-		assert(int(a.size()) == width);
-		assert(int(b.size()) == width);
+		log_assert(int(a.size()) == width);
+		log_assert(int(b.size()) == width);
 		for (int i = 0; i < width; i++)
 			if (a[i] <= RTLIL::State::S1 && b[i] <= RTLIL::State::S1 && a[i] != b[i])
 				return false;
diff --git a/kernel/calc.cc b/kernel/calc.cc
index 749589f20..b413760d1 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -24,7 +24,6 @@
 #include "kernel/log.h"
 #include "kernel/rtlil.h"
 #include "libs/bigint/BigIntegerLibrary.hh"
-#include <assert.h>
 
 static void extend(RTLIL::Const &arg, int width, bool is_signed)
 {
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 20d68d559..43c23add3 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -313,7 +313,7 @@ struct CellTypes
 			return ret;
 		}
 
-		assert(sel.bits.size() == 0);
+		log_assert(sel.bits.size() == 0);
 		return eval(cell, arg1, arg2);
 	}
 };
diff --git a/kernel/consteval.h b/kernel/consteval.h
index 1727d91cf..e5cae1022 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -72,7 +72,7 @@ struct ConstEval
 #ifndef NDEBUG
 		RTLIL::SigSpec current_val = values_map(sig);
 		for (int i = 0; i < SIZE(current_val); i++)
-			assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
+			log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
 #endif
 		values_map.add(sig, RTLIL::SigSpec(value));
 	}
@@ -87,7 +87,7 @@ struct ConstEval
 	{
 		RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
 
-		assert(cell->has("\\Y"));
+		log_assert(cell->has("\\Y"));
 		sig_y = values_map(assign_map(cell->get("\\Y")));
 		if (sig_y.is_fully_const())
 			return true;
@@ -133,7 +133,7 @@ struct ConstEval
 
 			std::vector<RTLIL::Const> y_values;
 
-			assert(y_candidates.size() > 0);
+			log_assert(y_candidates.size() > 0);
 			for (auto &yc : y_candidates) {
 				if (!eval(yc, undef, cell))
 					return false;
@@ -146,7 +146,7 @@ struct ConstEval
 
 				for (size_t i = 1; i < y_values.size(); i++) {
 					std::vector<RTLIL::State> &slave_bits = y_values.at(i).bits;
-					assert(master_bits.size() == slave_bits.size());
+					log_assert(master_bits.size() == slave_bits.size());
 					for (size_t j = 0; j < master_bits.size(); j++)
 						if (master_bits[j] != slave_bits[j])
 							master_bits[j] = RTLIL::State::Sx;
diff --git a/kernel/driver.cc b/kernel/driver.cc
index 380315e7c..a55fbbed5 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -327,7 +327,7 @@ static void shell(RTLIL::Design *design)
 		}
 
 		try {
-			assert(design->selection_stack.size() == 1);
+			log_assert(design->selection_stack.size() == 1);
 			Pass::call(design, command);
 		} catch (log_cmd_error_expection) {
 			while (design->selection_stack.size() > 1)
diff --git a/kernel/log.cc b/kernel/log.cc
index b8a47e1cf..8036b2360 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -18,6 +18,8 @@
  */
 
 #include "kernel/log.h"
+#include "kernel/rtlil.h"
+#include "kernel/register.h"
 #include "kernel/compatibility.h"
 #include "backends/ilang/ilang_backend.h"
 
@@ -29,9 +31,6 @@
 #include <vector>
 #include <list>
 
-// declared extern in log.h
-std::map<std::string, std::pair<std::string, int>> extra_coverage_data;
-
 std::vector<FILE*> log_files;
 FILE *log_errfile = NULL;
 bool log_time = false;
@@ -192,6 +191,10 @@ void log_flush()
 		fflush(f);
 }
 
+void log_dump_val_worker(RTLIL::SigSpec v) {
+	log("%s", log_signal(v));
+}
+
 const char *log_signal(const RTLIL::SigSpec &sig, bool autoint)
 {
 	char *ptr;
@@ -231,3 +234,51 @@ void log_cell(RTLIL::Cell *cell, std::string indent)
 	free(ptr);
 }
 
+// ---------------------------------------------------
+// This is the magic behind the code coverage counters
+// ---------------------------------------------------
+
+std::map<std::string, std::pair<std::string, int>> extra_coverage_data;
+
+void cover_extra(std::string parent, std::string id, bool increment) {
+	if (extra_coverage_data.count(id) == 0) {
+		for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++)
+			if (p->id == parent)
+				extra_coverage_data[id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
+		log_assert(extra_coverage_data.count(id));
+	}
+	if (increment)
+		extra_coverage_data[id].second++;
+}
+
+std::map<std::string, std::pair<std::string, int>> get_coverage_data()
+{
+	std::map<std::string, std::pair<std::string, int>> coverage_data;
+
+	for (auto &it : REGISTER_INTERN::pass_register) {
+		std::string key = stringf("passes.%s", it.first.c_str());
+		coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__);
+		coverage_data[key].second += it.second->call_counter;
+	}
+
+	for (auto &it : extra_coverage_data) {
+		if (coverage_data.count(it.first))
+			log("WARNING: found duplicate coverage id \"%s\".\n", it.first.c_str());
+		coverage_data[it.first].first = it.second.first;
+		coverage_data[it.first].second += it.second.second;
+	}
+
+	for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) {
+		if (coverage_data.count(p->id))
+			log("WARNING: found duplicate coverage id \"%s\".\n", p->id);
+		coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
+		coverage_data[p->id].second += p->counter;
+	}
+
+	for (auto &it : coverage_data)
+		if (!it.second.first.compare(0, strlen(YOSYS_SRC "/"), YOSYS_SRC "/"))
+			it.second.first = it.second.first.substr(strlen(YOSYS_SRC "/"));
+
+	return coverage_data;
+}
+
diff --git a/kernel/log.h b/kernel/log.h
index ca1e7c67c..3152fc5af 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -20,15 +20,15 @@
 #ifndef LOG_H
 #define LOG_H
 
-#include "kernel/rtlil.h"
-#include "kernel/register.h"
-
 #include <stdio.h>
 #include <string.h>
 #include <time.h>
 #include <sys/time.h>
 #include <sys/resource.h>
+
+#include <map>
 #include <vector>
+#include <string>
 
 #define S__LINE__sub2(x) #x
 #define S__LINE__sub1(x) S__LINE__sub2(x)
@@ -59,6 +59,11 @@ void log_pop();
 void log_reset_stack();
 void log_flush();
 
+namespace RTLIL {
+	struct SigSpec;
+	struct Cell;
+}
+
 const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);
 const char *log_id(std::string id);
 
@@ -96,47 +101,8 @@ extern "C" struct CoverData __stop_yosys_cover_list[];
 
 extern std::map<std::string, std::pair<std::string, int>> extra_coverage_data;
 
-static inline void cover_extra(std::string parent, std::string id, bool increment = true) {
-	if (extra_coverage_data.count(id) == 0) {
-		for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++)
-			if (p->id == parent)
-				extra_coverage_data[id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
-		log_assert(extra_coverage_data.count(id));
-	}
-	if (increment)
-		extra_coverage_data[id].second++;
-}
-
-static inline std::map<std::string, std::pair<std::string, int>> get_coverage_data()
-{
-	std::map<std::string, std::pair<std::string, int>> coverage_data;
-
-	for (auto &it : REGISTER_INTERN::pass_register) {
-		std::string key = stringf("passes.%s", it.first.c_str());
-		coverage_data[key].first = stringf("%s:%d:%s", __FILE__, __LINE__, __FUNCTION__);
-		coverage_data[key].second += it.second->call_counter;
-	}
-
-	for (auto &it : extra_coverage_data) {
-		if (coverage_data.count(it.first))
-			log("WARNING: found duplicate coverage id \"%s\".\n", it.first.c_str());
-		coverage_data[it.first].first = it.second.first;
-		coverage_data[it.first].second += it.second.second;
-	}
-
-	for (CoverData *p = __start_yosys_cover_list; p != __stop_yosys_cover_list; p++) {
-		if (coverage_data.count(p->id))
-			log("WARNING: found duplicate coverage id \"%s\".\n", p->id);
-		coverage_data[p->id].first = stringf("%s:%d:%s", p->file, p->line, p->func);
-		coverage_data[p->id].second += p->counter;
-	}
-
-	for (auto &it : coverage_data)
-		if (!it.second.first.compare(0, strlen(YOSYS_SRC "/"), YOSYS_SRC "/"))
-			it.second.first = it.second.first.substr(strlen(YOSYS_SRC "/"));
-
-	return coverage_data;
-}
+void cover_extra(std::string parent, std::string id, bool increment = true);
+std::map<std::string, std::pair<std::string, int>> get_coverage_data();
 
 #define cover_list(_id, ...) do { cover(_id); \
 	std::string r = cover_list_worker(_id, __VA_ARGS__); \
@@ -234,9 +200,9 @@ static inline void log_dump_val_worker(bool v) { log("%s", v ? "true" : "false")
 static inline void log_dump_val_worker(double v) { log("%f", v); }
 static inline void log_dump_val_worker(const char *v) { log("%s", v); }
 static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); }
-static inline void log_dump_val_worker(RTLIL::SigSpec v) { log("%s", log_signal(v)); }
 static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); }
 static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }
+void log_dump_val_worker(RTLIL::SigSpec v);
 
 template<typename T>
 static inline void log_dump_val_worker(T *ptr) { log("%p", ptr); }
diff --git a/kernel/register.cc b/kernel/register.cc
index 59667ac97..da3569831 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -20,7 +20,6 @@
 #include "kernel/compatibility.h"
 #include "kernel/register.h"
 #include "kernel/log.h"
-#include <assert.h>
 #include <string.h>
 #include <stdlib.h>
 #include <stdio.h>
@@ -50,7 +49,7 @@ Pass::Pass(std::string name, std::string short_help) : pass_name(name), short_he
 
 void Pass::run_register()
 {
-	assert(pass_register.count(pass_name) == 0);
+	log_assert(pass_register.count(pass_name) == 0);
 	pass_register[pass_name] = this;
 }
 
@@ -67,7 +66,7 @@ void Pass::done_register()
 	frontend_register.clear();
 	pass_register.clear();
 	backend_register.clear();
-	assert(first_queued_pass == NULL);
+	log_assert(first_queued_pass == NULL);
 }
 
 Pass::~Pass()
@@ -252,10 +251,10 @@ Frontend::Frontend(std::string name, std::string short_help) : Pass("read_"+name
 
 void Frontend::run_register()
 {
-	assert(pass_register.count(pass_name) == 0);
+	log_assert(pass_register.count(pass_name) == 0);
 	pass_register[pass_name] = this;
 
-	assert(frontend_register.count(frontend_name) == 0);
+	log_assert(frontend_register.count(frontend_name) == 0);
 	frontend_register[frontend_name] = this;
 }
 
@@ -265,7 +264,7 @@ Frontend::~Frontend()
 
 void Frontend::execute(std::vector<std::string> args, RTLIL::Design *design)
 {
-	assert(next_args.empty());
+	log_assert(next_args.empty());
 	do {
 		FILE *f = NULL;
 		next_args.clear();
@@ -383,10 +382,10 @@ Backend::Backend(std::string name, std::string short_help) : Pass("write_"+name,
 
 void Backend::run_register()
 {
-	assert(pass_register.count(pass_name) == 0);
+	log_assert(pass_register.count(pass_name) == 0);
 	pass_register[pass_name] = this;
 
-	assert(backend_register.count(backend_name) == 0);
+	log_assert(backend_register.count(backend_name) == 0);
 	backend_register[backend_name] = this;
 }
 
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 753c40090..783286182 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -23,7 +23,6 @@
 #include "frontends/verilog/verilog_frontend.h"
 #include "backends/ilang/ilang_backend.h"
 
-#include <assert.h>
 #include <string.h>
 #include <algorithm>
 
@@ -238,15 +237,15 @@ RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
 
 void RTLIL::Design::add(RTLIL::Module *module)
 {
-	assert(modules_.count(module->name) == 0);
-	assert(refcount_modules_ == 0);
+	log_assert(modules_.count(module->name) == 0);
+	log_assert(refcount_modules_ == 0);
 	modules_[module->name] = module;
 }
 
 RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
 {
-	assert(modules_.count(name) == 0);
-	assert(refcount_modules_ == 0);
+	log_assert(modules_.count(name) == 0);
+	log_assert(refcount_modules_ == 0);
 	modules_[name] = new RTLIL::Module;
 	modules_[name]->name = name;
 	return modules_[name];
@@ -254,7 +253,7 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
 
 void RTLIL::Design::remove(RTLIL::Module *module)
 {
-	assert(modules_.at(module->name) == module);
+	log_assert(modules_.at(module->name) == module);
 	modules_.erase(module->name);
 	delete module;
 }
@@ -263,8 +262,8 @@ void RTLIL::Design::check()
 {
 #ifndef NDEBUG
 	for (auto &it : modules_) {
-		assert(it.first == it.second->name);
-		assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(it.first == it.second->name);
+		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 		it.second->check();
 	}
 #endif
@@ -760,57 +759,57 @@ void RTLIL::Module::check()
 {
 #ifndef NDEBUG
 	for (auto &it : wires_) {
-		assert(it.first == it.second->name);
-		assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
-		assert(it.second->width >= 0);
-		assert(it.second->port_id >= 0);
+		log_assert(it.first == it.second->name);
+		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(it.second->width >= 0);
+		log_assert(it.second->port_id >= 0);
 		for (auto &it2 : it.second->attributes) {
-			assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+			log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 		}
 	}
 
 	for (auto &it : memories) {
-		assert(it.first == it.second->name);
-		assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
-		assert(it.second->width >= 0);
-		assert(it.second->size >= 0);
+		log_assert(it.first == it.second->name);
+		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(it.second->width >= 0);
+		log_assert(it.second->size >= 0);
 		for (auto &it2 : it.second->attributes) {
-			assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+			log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 		}
 	}
 
 	for (auto &it : cells_) {
-		assert(it.first == it.second->name);
-		assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
-		assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
+		log_assert(it.first == it.second->name);
+		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
 		for (auto &it2 : it.second->connections()) {
-			assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+			log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 			it2.second.check();
 		}
 		for (auto &it2 : it.second->attributes) {
-			assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+			log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 		}
 		for (auto &it2 : it.second->parameters) {
-			assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+			log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
 		}
 		InternalCellChecker checker(this, it.second);
 		checker.check();
 	}
 
 	for (auto &it : processes) {
-		assert(it.first == it.second->name);
-		assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(it.first == it.second->name);
+		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 		// FIXME: More checks here..
 	}
 
 	for (auto &it : connections_) {
-		assert(it.first.size() == it.second.size());
+		log_assert(it.first.size() == it.second.size());
 		it.first.check();
 		it.second.check();
 	}
 
 	for (auto &it : attributes) {
-		assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+		log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
 	}
 #endif
 }
@@ -934,7 +933,7 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
 
 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
 {
-	assert(wires_[wire->name] == wire);
+	log_assert(wires_[wire->name] == wire);
 	log_assert(refcount_wires_ == 0);
 	wires_.erase(wire->name);
 	wire->name = new_name;
@@ -943,7 +942,7 @@ void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
 
 void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
 {
-	assert(cells_[cell->name] == cell);
+	log_assert(cells_[cell->name] == cell);
 	log_assert(refcount_wires_ == 0);
 	cells_.erase(cell->name);
 	cell->name = new_name;
@@ -952,7 +951,7 @@ void RTLIL::Module::rename(RTLIL::Cell *cell, RTLIL::IdString new_name)
 
 void RTLIL::Module::rename(RTLIL::IdString old_name, RTLIL::IdString new_name)
 {
-	assert(count_id(old_name) != 0);
+	log_assert(count_id(old_name) != 0);
 	if (wires_.count(old_name))
 		rename(wires_.at(old_name), new_name);
 	else if (cells_.count(old_name))
@@ -1927,11 +1926,11 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
 	pattern.unpack();
 	with.unpack();
 
-	assert(other != NULL);
-	assert(width_ == other->width_);
+	log_assert(other != NULL);
+	log_assert(width_ == other->width_);
 	other->unpack();
 
-	assert(pattern.width_ == with.width_);
+	log_assert(pattern.width_ == with.width_);
 
 	std::map<RTLIL::SigBit, RTLIL::SigBit> pattern_map;
 	for (int i = 0; i < SIZE(pattern.bits_); i++)
@@ -1966,7 +1965,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
 	unpack();
 
 	if (other != NULL) {
-		assert(width_ == other->width_);
+		log_assert(width_ == other->width_);
 		other->unpack();
 	}
 
@@ -2005,7 +2004,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(RTLIL::SigSpec pattern, const RTLIL::SigS
 	if (other != NULL)
 		other->pack();
 
-	assert(other == NULL || width_ == other->width_);
+	log_assert(other == NULL || width_ == other->width_);
 
 	std::set<RTLIL::SigBit> pat = pattern.to_sigbit_set();
 	std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
@@ -2033,9 +2032,9 @@ void RTLIL::SigSpec::replace(int offset, const RTLIL::SigSpec &with)
 	unpack();
 	with.unpack();
 
-	assert(offset >= 0);
-	assert(with.width_ >= 0);
-	assert(offset+with.width_ <= width_);
+	log_assert(offset >= 0);
+	log_assert(with.width_ >= 0);
+	log_assert(offset+with.width_ <= width_);
 
 	for (int i = 0; i < with.width_; i++)
 		bits_.at(offset + i) = with.bits_.at(i);
@@ -2085,9 +2084,9 @@ void RTLIL::SigSpec::remove(int offset, int length)
 
 	unpack();
 
-	assert(offset >= 0);
-	assert(length >= 0);
-	assert(offset + length <= width_);
+	log_assert(offset >= 0);
+	log_assert(length >= 0);
+	log_assert(offset + length <= width_);
 
 	bits_.erase(bits_.begin() + offset, bits_.begin() + offset + length);
 	width_ = bits_.size();
@@ -2236,28 +2235,28 @@ void RTLIL::SigSpec::check() const
 			const RTLIL::SigChunk chunk = chunks_[i];
 			if (chunk.wire == NULL) {
 				if (i > 0)
-					assert(chunks_[i-1].wire != NULL);
-				assert(chunk.offset == 0);
-				assert(chunk.data.bits.size() == (size_t)chunk.width);
+					log_assert(chunks_[i-1].wire != NULL);
+				log_assert(chunk.offset == 0);
+				log_assert(chunk.data.bits.size() == (size_t)chunk.width);
 			} else {
 				if (i > 0 && chunks_[i-1].wire == chunk.wire)
-					assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
-				assert(chunk.offset >= 0);
-				assert(chunk.width >= 0);
-				assert(chunk.offset + chunk.width <= chunk.wire->width);
-				assert(chunk.data.bits.size() == 0);
+					log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
+				log_assert(chunk.offset >= 0);
+				log_assert(chunk.width >= 0);
+				log_assert(chunk.offset + chunk.width <= chunk.wire->width);
+				log_assert(chunk.data.bits.size() == 0);
 			}
 			w += chunk.width;
 		}
-		assert(w == width_);
-		assert(bits_.empty());
+		log_assert(w == width_);
+		log_assert(bits_.empty());
 	}
 	else
 	{
 		cover("kernel.rtlil.sigspec.check.unpacked");
 
-		assert(width_ == SIZE(bits_));
-		assert(chunks_.empty());
+		log_assert(width_ == SIZE(bits_));
+		log_assert(chunks_.empty());
 	}
 }
 #endif
@@ -2402,7 +2401,7 @@ bool RTLIL::SigSpec::as_bool() const
 	cover("kernel.rtlil.sigspec.as_bool");
 
 	pack();
-	assert(is_fully_const() && SIZE(chunks_) <= 1);
+	log_assert(is_fully_const() && SIZE(chunks_) <= 1);
 	if (width_)
 		return chunks_[0].data.as_bool();
 	return false;
@@ -2413,7 +2412,7 @@ int RTLIL::SigSpec::as_int() const
 	cover("kernel.rtlil.sigspec.as_int");
 
 	pack();
-	assert(is_fully_const() && SIZE(chunks_) <= 1);
+	log_assert(is_fully_const() && SIZE(chunks_) <= 1);
 	if (width_)
 		return chunks_[0].data.as_int();
 	return 0;
@@ -2441,7 +2440,7 @@ RTLIL::Const RTLIL::SigSpec::as_const() const
 	cover("kernel.rtlil.sigspec.as_const");
 
 	pack();
-	assert(is_fully_const() && SIZE(chunks_) <= 1);
+	log_assert(is_fully_const() && SIZE(chunks_) <= 1);
 	if (width_)
 		return chunks_[0].data;
 	return RTLIL::Const();
@@ -2452,7 +2451,7 @@ RTLIL::Wire *RTLIL::SigSpec::as_wire() const
 	cover("kernel.rtlil.sigspec.as_wire");
 
 	pack();
-	assert(is_wire());
+	log_assert(is_wire());
 	return chunks_[0].wire;
 }
 
@@ -2461,7 +2460,7 @@ RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
 	cover("kernel.rtlil.sigspec.as_chunk");
 
 	pack();
-	assert(is_chunk());
+	log_assert(is_chunk());
 	return chunks_[0];
 }
 
@@ -2471,7 +2470,7 @@ bool RTLIL::SigSpec::match(std::string pattern) const
 
 	pack();
 	std::string str = as_string();
-	assert(pattern.size() == str.size());
+	log_assert(pattern.size() == str.size());
 
 	for (size_t i = 0; i < pattern.size(); i++) {
 		if (pattern[i] == ' ')
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 331ea3770..d78a6df22 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -24,8 +24,8 @@
 #include <set>
 #include <vector>
 #include <string>
-#include <assert.h>
 
+#include "kernel/log.h"
 #include <initializer_list>
 
 // various helpers (unrelated to RTLIL)
@@ -107,7 +107,7 @@ namespace RTLIL
 			return std::string(*this) < std::string(rhs);
 		}
 		void check() const {
-			assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\')));
+			log_assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\')));
 		}
 	};
 #endif
@@ -242,7 +242,7 @@ namespace RTLIL
 		}
 
 		inline T operator*() const {
-			assert(list_p != nullptr);
+			log_assert(list_p != nullptr);
 			return it->second;
 		}
 
@@ -253,7 +253,7 @@ namespace RTLIL
 		}
 
 		inline void operator++() {
-			assert(list_p != nullptr);
+			log_assert(list_p != nullptr);
 			if (++it == list_p->end()) {
 				(*refcount_p)--;
 				list_p = nullptr;
@@ -677,9 +677,9 @@ struct RTLIL::SigBit
 
 	SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { }
 	SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { }
-	SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { assert(wire && wire->width == 1); }
-	SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { assert(wire); }
-	SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { assert(chunk.width == 1); }
+	SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { log_assert(wire && wire->width == 1); }
+	SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { log_assert(wire); }
+	SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { log_assert(chunk.width == 1); }
 	SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { }
 	SigBit(const RTLIL::SigSpec &sig);
 
@@ -856,7 +856,7 @@ inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {
 }
 
 inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
-	assert(sig.size() == 1 && sig.chunks().size() == 1);
+	log_assert(sig.size() == 1 && sig.chunks().size() == 1);
 	*this = SigBit(sig.chunks().front());
 }
 
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 6a288a8da..27a29cb57 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -116,7 +116,7 @@ struct SatGen
 		if (timestep_rhs < 0)
 			timestep_rhs = timestep_lhs;
 
-		assert(lhs.size() == rhs.size());
+		log_assert(lhs.size() == rhs.size());
 
 		std::vector<int> vec_lhs = importSigSpec(lhs, timestep_lhs);
 		std::vector<int> vec_rhs = importSigSpec(rhs, timestep_rhs);
@@ -163,14 +163,14 @@ struct SatGen
 
 	void undefGating(std::vector<int> &vec_y, std::vector<int> &vec_yy, std::vector<int> &vec_undef)
 	{
-		assert(model_undef);
-		assert(vec_y.size() == vec_yy.size());
+		log_assert(model_undef);
+		log_assert(vec_y.size() == vec_yy.size());
 		if (vec_y.size() > vec_undef.size()) {
 			std::vector<int> trunc_y(vec_y.begin(), vec_y.begin() + vec_undef.size());
 			std::vector<int> trunc_yy(vec_yy.begin(), vec_yy.begin() + vec_undef.size());
 			ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(trunc_y, trunc_yy))));
 		} else {
-			assert(vec_y.size() == vec_undef.size());
+			log_assert(vec_y.size() == vec_undef.size());
 			ez->assume(ez->expression(ezSAT::OpAnd, ez->vec_or(vec_undef, ez->vec_iff(vec_y, vec_yy))));
 		}
 	}
diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 52e4aa0fb..79a9fb238 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -22,7 +22,6 @@
 
 #include "kernel/rtlil.h"
 #include "kernel/log.h"
-#include <assert.h>
 #include <set>
 
 struct SigPool
@@ -67,7 +66,7 @@ struct SigPool
 
 	void expand(RTLIL::SigSpec from, RTLIL::SigSpec to)
 	{
-		assert(SIZE(from) == SIZE(to));
+		log_assert(SIZE(from) == SIZE(to));
 		for (int i = 0; i < SIZE(from); i++) {
 			bitDef_t bit_from(from[i]), bit_to(to[i]);
 			if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)
@@ -304,11 +303,11 @@ struct SigMap
 	// internal helper function
 	void merge_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2)
 	{
-		assert(bit1.wire != NULL && bit2.wire != NULL);
+		log_assert(bit1.wire != NULL && bit2.wire != NULL);
 
 		shared_bit_data_t *bd1 = bits[bit1];
 		shared_bit_data_t *bd2 = bits[bit2];
-		assert(bd1 != NULL && bd2 != NULL);
+		log_assert(bd1 != NULL && bd2 != NULL);
 
 		if (bd1 == bd2)
 			return;
@@ -333,8 +332,8 @@ struct SigMap
 	// internal helper function
 	void set_bit(const RTLIL::SigBit &bit1, const RTLIL::SigBit &bit2)
 	{
-		assert(bit1.wire != NULL);
-		assert(bits.count(bit1) > 0);
+		log_assert(bit1.wire != NULL);
+		log_assert(bits.count(bit1) > 0);
 		bits[bit1]->map_to = bit2;
 	}
 
@@ -347,7 +346,7 @@ struct SigMap
 
 	void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
 	{
-		assert(SIZE(from) == SIZE(to));
+		log_assert(SIZE(from) == SIZE(to));
 
 		for (int i = 0; i < SIZE(from); i++)
 		{
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 03fc9f937..d2be7dcf1 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -39,7 +39,6 @@
 #include "kernel/log.h"
 #include <unistd.h>
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 #include <dirent.h>
@@ -273,7 +272,7 @@ static void handle_loops()
 		// log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit));
 
 		for (int id2 : edges[id]) {
-			assert(in_edges_count[id2] > 0);
+			log_assert(in_edges_count[id2] > 0);
 			if (--in_edges_count[id2] == 0)
 				workpool.insert(id2);
 		}
@@ -331,7 +330,7 @@ static void handle_loops()
 			int id3 = map_signal(RTLIL::SigSpec(wire));
 			signal_list[id1].is_port = true;
 			signal_list[id3].is_port = true;
-			assert(id3 == int(in_edges_count.size()));
+			log_assert(id3 == int(in_edges_count.size()));
 			in_edges_count.push_back(0);
 			workpool.insert(id3);
 
@@ -778,7 +777,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 					for (auto &c : conn.second.chunks()) {
 						if (c.width == 0)
 							continue;
-						assert(c.width == 1);
+						log_assert(c.width == 1);
 						newsig.append(module->wires_[remap_name(c.wire->name)]);
 					}
 					cell->set(conn.first, newsig);
@@ -831,7 +830,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
 
 		struct dirent **namelist;
 		int n = scandir(tempdir_name, &namelist, 0, alphasort);
-		assert(n >= 0);
+		log_assert(n >= 0);
 		for (int i = 0; i < n; i++) {
 			if (strcmp(namelist[i]->d_name, ".") && strcmp(namelist[i]->d_name, "..")) {
 				if (asprintf(&p, "%s/%s", tempdir_name, namelist[i]->d_name) < 0) log_abort();
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index 1fa1b4c9c..8c039e3e9 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -51,7 +51,7 @@ struct SccWorker
 
 	void run(RTLIL::Cell *cell, int depth, int maxDepth)
 	{
-		assert(workQueue.count(cell) > 0);
+		log_assert(workQueue.count(cell) > 0);
 
 		workQueue.erase(cell);
 		cellLabels[cell] = std::pair<int, int>(labelCounter, labelCounter);
@@ -166,7 +166,7 @@ struct SccWorker
 
 		while (workQueue.size() > 0) {
 			RTLIL::Cell *cell = *workQueue.begin();
-			assert(cellStack.size() == 0);
+			log_assert(cellStack.size() == 0);
 			cellDepth.clear();
 			run(cell, 0, maxDepth);
 		}
@@ -290,7 +290,7 @@ struct SccPass : public Pass {
 			}
 
 		if (selectMode) {
-			assert(origSelectPos >= 0);
+			log_assert(origSelectPos >= 0);
 			design->selection_stack[origSelectPos] = newSelection;
 			design->selection_stack[origSelectPos].optimize(design);
 		}
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 85c52277c..bbfa396ba 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1120,7 +1120,7 @@ struct SelectPass : public Pass {
 			work_stack.pop_back();
 		}
 
-		assert(design->selection_stack.size() > 0);
+		log_assert(design->selection_stack.size() > 0);
 
 		if (clear_mode) {
 			design->selection_stack.back() = RTLIL::Selection(true);
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 7ab1daf00..a2dd8051b 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -202,7 +202,7 @@ struct ShowWorker
 			for (int i = int(sig.chunks().size())-1; i >= 0; i--) {
 				const RTLIL::SigChunk &c = sig.chunks().at(i);
 				net = gen_signode_simple(c, false);
-				assert(!net.empty());
+				log_assert(!net.empty());
 				if (driver) {
 					label_string += stringf("<s%d> %d:%d - %d:%d |", i, pos, pos-c.width+1, c.offset+c.width-1, c.offset);
 					net_conn_map[net].in.insert(stringf("x%d:s%d", idx, i));
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index f107366d6..2da4794eb 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -157,9 +157,9 @@ struct FsmExpand
 			A.replace(input_sig, RTLIL::SigSpec(in_val));
 			B.replace(input_sig, RTLIL::SigSpec(in_val));
 			S.replace(input_sig, RTLIL::SigSpec(in_val));
-			assert(A.is_fully_const());
-			assert(B.is_fully_const());
-			assert(S.is_fully_const());
+			log_assert(A.is_fully_const());
+			log_assert(B.is_fully_const());
+			log_assert(S.is_fully_const());
 			truth_tab.push_back(ct.eval(cell, A.as_const(), B.as_const(), S.as_const()));
 		}
 
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 99352b10a..6da468321 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -109,7 +109,7 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d
 	RTLIL::SigSpec undef, constval;
 
 	if (ce.eval(ctrl_out, undef) && ce.eval(dff_in, undef)) {
-		assert(ctrl_out.is_fully_const() && dff_in.is_fully_const());
+		log_assert(ctrl_out.is_fully_const() && dff_in.is_fully_const());
 		FsmData::transition_t tr;
 		tr.state_in = state_in;
 		tr.state_out = states[ce.values_map(ce.assign_map(dff_in)).as_const()];
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 8aec25eba..c869ec729 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -98,7 +98,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 					generate_port_decl_t d = decl;
 					d.portname = portname;
 					d.index = *indices.begin();
-					assert(!indices.empty());
+					log_assert(!indices.empty());
 					indices.erase(d.index);
 					ports[d.index-1] = d;
 					portwidths[d.portname] = std::max(portwidths[d.portname], 1);
@@ -110,7 +110,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 			portnames.erase(portname);
 		}
 
-		assert(indices.empty());
+		log_assert(indices.empty());
 
 		RTLIL::Module *mod = new RTLIL::Module;
 		mod->name = celltype;
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index d32b5e1d3..84c6b9161 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -171,7 +171,7 @@ struct SubmodWorker
 			for (auto &conn : new_cell->connections_)
 				for (auto &bit : conn.second)
 					if (bit.wire != NULL) {
-						assert(wire_flags.count(bit.wire) > 0);
+						log_assert(wire_flags.count(bit.wire) > 0);
 						bit.wire = wire_flags[bit.wire].new_wire;
 					}
 			log("  cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index d2803ae78..40c68abc1 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -22,7 +22,6 @@
 #include <sstream>
 #include <algorithm>
 #include <stdlib.h>
-#include <assert.h>
 
 static bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
 {
@@ -136,12 +135,12 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
 	mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
 
-	assert(sig_wr_clk.size() == wr_ports);
-	assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
-	assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
-	assert(sig_wr_addr.size() == wr_ports * addr_bits);
-	assert(sig_wr_data.size() == wr_ports * memory->width);
-	assert(sig_wr_en.size() == wr_ports * memory->width);
+	log_assert(sig_wr_clk.size() == wr_ports);
+	log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
+	log_assert(sig_wr_clk_polarity.size() == wr_ports && sig_wr_clk_polarity.is_fully_const());
+	log_assert(sig_wr_addr.size() == wr_ports * addr_bits);
+	log_assert(sig_wr_data.size() == wr_ports * memory->width);
+	log_assert(sig_wr_en.size() == wr_ports * memory->width);
 
 	mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
 	mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0);
@@ -152,11 +151,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	mem->set("\\WR_DATA", sig_wr_data);
 	mem->set("\\WR_EN", sig_wr_en);
 
-	assert(sig_rd_clk.size() == rd_ports);
-	assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
-	assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
-	assert(sig_rd_addr.size() == rd_ports * addr_bits);
-	assert(sig_rd_data.size() == rd_ports * memory->width);
+	log_assert(sig_rd_clk.size() == rd_ports);
+	log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
+	log_assert(sig_rd_clk_polarity.size() == rd_ports && sig_rd_clk_polarity.is_fully_const());
+	log_assert(sig_rd_addr.size() == rd_ports * addr_bits);
+	log_assert(sig_rd_data.size() == rd_ports * memory->width);
 
 	mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
 	mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0);
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 85249142e..325056170 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -20,7 +20,6 @@
 #include "kernel/register.h"
 #include "kernel/log.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <sstream>
 
 static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index 53394b19a..49291656c 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -22,7 +22,6 @@
 #include <sstream>
 #include <set>
 #include <stdlib.h>
-#include <assert.h>
 
 static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
 {
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index d2b9c0eeb..cdf7db04b 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -22,7 +22,6 @@
 #include <sstream>
 #include <algorithm>
 #include <stdlib.h>
-#include <assert.h>
 
 static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 {
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 6c20bddbb..4182c6f5d 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -23,7 +23,6 @@
 #include "kernel/log.h"
 #include "kernel/celltypes.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <set>
 
@@ -227,7 +226,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 			if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) {
 				maybe_del_wires.push_back(wire);
 			} else {
-				assert(SIZE(s1) == SIZE(s2));
+				log_assert(SIZE(s1) == SIZE(s2));
 				RTLIL::SigSig new_conn;
 				for (int i = 0; i < SIZE(s1); i++)
 					if (s1[i] != s2[i]) {
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 7578f1927..254fe5bb4 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -24,7 +24,6 @@
 #include "kernel/toposort.h"
 #include "kernel/log.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <algorithm>
 
@@ -495,7 +494,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			RTLIL::SigSpec new_a, new_b;
 
-			assert(SIZE(a) == SIZE(b));
+			log_assert(SIZE(a) == SIZE(b));
 			for (int i = 0; i < SIZE(a); i++) {
 				if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
 					cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type);
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 73baaf900..de12542dc 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -23,7 +23,6 @@
 #include "kernel/log.h"
 #include "kernel/celltypes.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <set>
 
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index b2b7cc8b9..8aadd1f23 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -24,7 +24,6 @@
 #include "kernel/celltypes.h"
 #include "libs/sha1/sha1.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <set>
 
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 45130229f..ad6e1a746 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -24,7 +24,6 @@
 #include "kernel/celltypes.h"
 #include "libs/sha1/sha1.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <set>
 
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index dc310bde0..91cafe3be 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -24,7 +24,6 @@
 #include <sstream>
 #include <stdlib.h>
 #include <stdio.h>
-#include <assert.h>
 
 static RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
 {
@@ -288,7 +287,7 @@ static void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 					inputs.append(it->signal);
 					compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0);
 				}
-				assert(inputs.size() == compare.size());
+				log_assert(inputs.size() == compare.size());
 
 				RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne");
 				cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1);
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index 99498505f..c72840c02 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -25,7 +25,7 @@
 
 static void proc_get_const(RTLIL::SigSpec &sig, RTLIL::CaseRule &rule)
 {
-	assert(rule.compare.size() == 0);
+	log_assert(rule.compare.size() == 0);
 
 	while (1) {
 		RTLIL::SigSpec tmp = sig;
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index fb49182c2..e7661245e 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -23,7 +23,6 @@
 #include <sstream>
 #include <stdlib.h>
 #include <stdio.h>
-#include <assert.h>
 
 static RTLIL::SigSpec find_any_lvalue(const RTLIL::CaseRule *cs)
 {
@@ -67,7 +66,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 		RTLIL::SigSpec sig = signal;
 
 		// get rid of don't-care bits
-		assert(sig.size() == comp.size());
+		log_assert(sig.size() == comp.size());
 		for (int i = 0; i < comp.size(); i++)
 			if (comp[i] == RTLIL::State::Sa) {
 				sig.remove(i);
@@ -125,7 +124,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
 static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::SigSpec else_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw)
 {
-	assert(when_signal.size() == else_signal.size());
+	log_assert(when_signal.size() == else_signal.size());
 
 	std::stringstream sstr;
 	sstr << "$procmux$" << (RTLIL::autoidx++);
@@ -138,7 +137,7 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
 	if (ctrl_sig.size() == 0)
 		return when_signal;
-	assert(ctrl_sig.size() == 1);
+	log_assert(ctrl_sig.size() == 1);
 
 	// prepare multiplexer output signal
 	RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size());
@@ -159,11 +158,11 @@ static RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
 static void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw)
 {
-	assert(last_mux_cell != NULL);
-	assert(when_signal.size() == last_mux_cell->get("\\A").size());
+	log_assert(last_mux_cell != NULL);
+	log_assert(when_signal.size() == last_mux_cell->get("\\A").size());
 
 	RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw);
-	assert(ctrl_sig.size() == 1);
+	log_assert(ctrl_sig.size() == 1);
 	last_mux_cell->type = "$pmux";
 
 	RTLIL::SigSpec new_s = last_mux_cell->get("\\S");
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc
index 9e5f413a2..61844d5eb 100644
--- a/passes/proc/proc_rmdead.cc
+++ b/passes/proc/proc_rmdead.cc
@@ -23,7 +23,6 @@
 #include <sstream>
 #include <stdlib.h>
 #include <stdio.h>
-#include <assert.h>
 #include <set>
 
 static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index dce312065..430628e46 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -335,7 +335,7 @@ struct SatHelper
 
 	int setup_proof(int timestep = -1)
 	{
-		assert(prove.size() || prove_x.size() || prove_asserts);
+		log_assert(prove.size() || prove_x.size() || prove_asserts);
 
 		RTLIL::SigSpec big_lhs, big_rhs;
 		std::vector<int> prove_bits;
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 8587f53b0..9c5fa7f71 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -23,7 +23,6 @@
 #include "libs/subcircuit/subcircuit.h"
 #include <algorithm>
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 
@@ -100,7 +99,7 @@ namespace
 			RTLIL::Cell *haystackCell = (RTLIL::Cell*) haystackUserData;
 
 			if (!needleCell || !haystackCell) {
-				assert(!needleCell && !haystackCell);
+				log_assert(!needleCell && !haystackCell);
 				return true;
 			}
 
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index b327ba832..5c3e4c68f 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -21,7 +21,6 @@
 #include "kernel/sigtools.h"
 #include "kernel/log.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 79e70a59c..5a69baca5 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -23,7 +23,6 @@
 #include "kernel/toposort.h"
 #include "kernel/log.h"
 #include <stdlib.h>
-#include <assert.h>
 #include <stdio.h>
 #include <string.h>
 
@@ -47,7 +46,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
 		if (chunk.wire != NULL) {
 			std::string wire_name = chunk.wire->name;
 			apply_prefix(prefix, wire_name);
-			assert(module->wires_.count(wire_name) > 0);
+			log_assert(module->wires_.count(wire_name) > 0);
 			chunk.wire = module->wires_[wire_name];
 		}
 	sig = chunks;
@@ -167,7 +166,7 @@ struct TechmapWorker
 				c.second.remove(c.first.size(), c.second.size() - c.first.size());
 			if (c.second.size() < c.first.size())
 				c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
-			assert(c.first.size() == c.second.size());
+			log_assert(c.first.size() == c.second.size());
 			if (flatten_mode) {
 				// more conservative approach:
 				// connect internal and external wires
@@ -427,7 +426,7 @@ struct TechmapWorker
 							const char *q = strrchr(p+1, '.');
 							q = q ? q : p+1;
 
-							assert(!strncmp(q, "_TECHMAP_DO_", 12));
+							log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
 							std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
 							while (tpl->wires_.count(new_name))
 								new_name += "_";