From: Gabe Black Date: Wed, 27 Feb 2008 04:38:01 +0000 (-0500) Subject: X86: Get PCI config space to work, and adjust address space prefix numbering scheme. X-Git-Tag: m5_2.0_beta5~3^2~7 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7bde0285e50e3903e38dd9e6fd59ea4a98f41079;p=gem5.git X86: Get PCI config space to work, and adjust address space prefix numbering scheme. --HG-- extra : convert_revision : 2b382f478ee8cde3a35aa4c105196f200bc7afa6 --- diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 6d7634106..44c13ef78 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -156,7 +156,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc = None): return self def x86IOAddress(port): - IO_address_space_base = 0x1000000000000000 + IO_address_space_base = 0x8000000000000000 return IO_address_space_base + port; def makeLinuxX86System(mem_mode, mdesc = None): @@ -189,6 +189,7 @@ def makeLinuxX86System(mem_mode, mdesc = None): # Platform self.opteron = Opteron() + self.opteron.attachIO(self.iobus) self.intrctrl = IntrControl() diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh index 36b953526..2bf647150 100644 --- a/src/arch/x86/miscregs.hh +++ b/src/arch/x86/miscregs.hh @@ -339,6 +339,8 @@ namespace X86ISA //XXX Add "Model-Specific Registers" + MISCREG_PCI_CONFIG_ADDRESS, + NUM_MISCREGS }; diff --git a/src/arch/x86/mmaped_ipr.hh b/src/arch/x86/mmaped_ipr.hh index 9184ec4dc..36c0baaca 100644 --- a/src/arch/x86/mmaped_ipr.hh +++ b/src/arch/x86/mmaped_ipr.hh @@ -64,6 +64,7 @@ * ISA-specific helper functions for memory mapped IPR accesses. */ +#include "arch/x86/miscregs.hh" #include "config/full_system.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" @@ -88,8 +89,13 @@ namespace X86ISA #if !FULL_SYSTEM panic("Shouldn't have a memory mapped register in SE\n"); #else - xc->setMiscReg(pkt->getAddr() / sizeof(MiscReg), - gtoh(pkt->get())); + MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg)); + if (index == MISCREG_PCI_CONFIG_ADDRESS) { + xc->setMiscReg(index, gtoh(pkt->get())); + } else { + xc->setMiscReg(pkt->getAddr() / sizeof(MiscReg), + gtoh(pkt->get())); + } #endif return xc->getCpuPtr()->ticks(1); } diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 2e6ea4a22..acac3081a 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -76,7 +76,7 @@ namespace X86ISA { -TLB::TLB(const Params *p) : SimObject(p), size(p->size) +TLB::TLB(const Params *p) : SimObject(p), configAddress(0), size(p->size) { tlb = new TlbEntry[size]; std::memset(tlb, 0, sizeof(TlbEntry) * size); @@ -147,6 +147,12 @@ TLB::invalidateAll() } } +void +TLB::setConfigAddress(uint32_t addr) +{ + configAddress = addr; +} + void TLB::invalidateNonGlobal() { @@ -478,7 +484,19 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute) // Make sure the address fits in the expected 16 bit IO address // space. assert(!(IOPort & ~0xFFFF)); - req->setPaddr(PhysAddrPrefixIO | IOPort); + if (IOPort == 0xCF8 && req->getSize() == 4) { + req->setMmapedIpr(true); + req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); + } else if ((IOPort & ~mask(2)) == 0xCFC) { + Addr configAddress = + tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); + if (bits(configAddress, 31, 31)) { + req->setPaddr(PhysAddrPrefixPciConfig | + bits(configAddress, 30, 0)); + } + } else { + req->setPaddr(PhysAddrPrefixIO | IOPort); + } return NoFault; } else { panic("Access to unrecognized internal address space %#x.\n", diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index a361c2291..d08d6fa68 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -90,6 +90,7 @@ namespace X86ISA friend class FakeDTLBFault; bool _allowNX; + uint32_t configAddress; public: bool allowNX() const @@ -104,6 +105,8 @@ namespace X86ISA TlbEntry *lookup(Addr va, bool update_lru = true); + void setConfigAddress(uint32_t addr); + #if FULL_SYSTEM protected: diff --git a/src/arch/x86/x86_traits.hh b/src/arch/x86/x86_traits.hh index dc71de500..d605ce218 100644 --- a/src/arch/x86/x86_traits.hh +++ b/src/arch/x86/x86_traits.hh @@ -88,7 +88,8 @@ namespace X86ISA const Addr IntAddrPrefixMSR = ULL(0x200000000); const Addr IntAddrPrefixIO = ULL(0x300000000); - const Addr PhysAddrPrefixIO = ULL(0x1000000000000000); + const Addr PhysAddrPrefixIO = ULL(0x8000000000000000); + const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000); } #endif //__ARCH_X86_X86TRAITS_HH__ diff --git a/src/dev/x86/Opteron.py b/src/dev/x86/Opteron.py index 435ecccb6..cb015e2e7 100644 --- a/src/dev/x86/Opteron.py +++ b/src/dev/x86/Opteron.py @@ -3,8 +3,16 @@ from m5.proxy import * from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr from Uart import Uart8250 from Platform import Platform +from Pci import PciConfigAll from SimConsole import SimConsole class Opteron(Platform): type = 'Opteron' system = Param.System(Parent.any, "system") + + pciconfig = PciConfigAll() + + def attachIO(self, bus): + self.pciconfig.pio = bus.default + bus.responder_set = True + bus.responder = self.pciconfig diff --git a/src/dev/x86/opteron.cc b/src/dev/x86/opteron.cc index df28e58de..ba46f2dfa 100644 --- a/src/dev/x86/opteron.cc +++ b/src/dev/x86/opteron.cc @@ -36,6 +36,7 @@ #include #include +#include "arch/x86/x86_traits.hh" #include "cpu/intr_control.hh" #include "dev/simconsole.hh" #include "dev/x86/opteron.hh" @@ -95,8 +96,10 @@ Opteron::pciToDma(Addr pciAddr) const Addr Opteron::calcConfigAddr(int bus, int dev, int func) { - panic("Need implementation\n"); - M5_DUMMY_RETURN + assert(func < 8); + assert(dev < 32); + assert(bus == 0); + return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11)); } Opteron *