From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Thu, 2 Jul 2020 11:22:32 +0000 (+0200)
Subject: Flatten specific parts of the designs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c18424d7f2666628f665f1f9e5ce3e3021a640b;p=gram.git

Flatten specific parts of the designs
---

diff --git a/gram/simulation/simsoc.ys b/gram/simulation/simsoc.ys
index 35e11ea..bdd7d3d 100644
--- a/gram/simulation/simsoc.ys
+++ b/gram/simulation/simsoc.ys
@@ -12,5 +12,9 @@ pmuxtree
 memory_collect
 extract_fa -v
 clean
+flatten \ub
+flatten \decoder
+flatten \arbiter
+flatten \sysclk
 opt -fine -full
 write_verilog -norename build_simsoc/top.v