From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 25 Apr 2021 13:50:39 +0000 (-0300)
Subject: Match CR size on ISACaller mtcrf test case
X-Git-Tag: 0.0.3~108
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c381349b8a3e94c3cad303138c0c541ad7c20ba;p=openpower-isa.git

Match CR size on ISACaller mtcrf test case

The underlying register for CR seems to be 64 bits for some reason. See:
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/caller.py;h=2f9dfa8746625f74fccaf9cd8a86f5503837009d;hb=HEAD#l495
---

diff --git a/src/openpower/decoder/isa/test_caller.py b/src/openpower/decoder/isa/test_caller.py
index 00856352..ce934609 100644
--- a/src/openpower/decoder/isa/test_caller.py
+++ b/src/openpower/decoder/isa/test_caller.py
@@ -317,7 +317,7 @@ class DecoderTestCase(FHDLTestCase):
             print("cr%d", sim.crl[i])
             self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
             # check CR itself
-            self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 32))
+            self.assertEqual(sim.cr, SelectableInt(expected << ((7-i)*4), 64))
 
     def run_tst_program(self, prog, initial_regs=[0] * 32):
         simulator = run_tst(prog, initial_regs)