From: lkcl <lkcl@web>
Date: Sat, 2 Apr 2022 11:34:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2933
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c3becdf7f5536dc8aa0fb0857a5f032cd612d5d;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 5259668ac..b670c76e9 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -8,7 +8,11 @@ considered completely separate and distinct from
 standard scalar OpenPOWER-approved v3.0B branches.
 **v3.0B branches are in no way impacted, altered,
 changed or modified in any way, shape or form by
-the SVP64 Vectorised Variants**.
+the SVP64 Vectorised Variants**.  It is
+extremely important to note that this is the one
+sole semi-exception in SVPY4 to `Scalar Identity Behaviour`.
+SVP64 Branches contain additional modes that are useful
+for scalar operations (i.e. even when VL=1).
 
 Links
 
@@ -467,6 +471,27 @@ if ctr_ok & cond_ok then
 if LK then LR  <-iea  CIA + 4
 ```
 
+Simplified pseudocode including LRu and CTR skipping, which illustrates
+clearly that SVP64 Scalar Branches (VL=1) are **not** identical to
+v3.0B Scalar Branches.
+
+```
+if (mode_is_64bit) then M <- 0
+else M <- 32
+cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
+ctrdec = ¬BO[2]
+if CTRtest & (cond_ok ^ CTi) then
+   ctrdec = 0b0
+if ctrdec then CTR <- CTR - 1
+ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
+lr_ok <- SVRMmode.LRu
+if ctr_ok & cond_ok then
+  if AA then NIA <-iea EXTS(BD || 0b00)
+  else       NIA <-iea CIA + EXTS(BD || 0b00)
+  lr_ok <- 0b1
+if LK & lr_ok then LR <-iea CIA + 4
+```
+
 Pseudocode for Horizontal-First Mode:
 
 ```
@@ -540,25 +565,6 @@ if VLSET and cond_ok = VSb then
         SVSTATE.VL = new_srcstep
 ```
 
-v3.0B branch pseudocode including LRu and CTR skipping
-
-```
-if (mode_is_64bit) then M <- 0
-else M <- 32
-cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1])
-ctrdec = ¬BO[2]
-if CTRtest & (cond_ok ^ CTi) then
-   ctrdec = 0b0
-if ctrdec then CTR <- CTR - 1
-ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
-lr_ok <- SVRMmode.LRu
-if ctr_ok & cond_ok then
-  if AA then NIA <-iea EXTS(BD || 0b00)
-  else       NIA <-iea CIA + EXTS(BD || 0b00)
-  lr_ok <- 0b1
-if LK & lr_ok then LR <-iea CIA + 4
-```
-
 # Example Shader code
 
 ```