From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 10 Apr 2021 14:46:20 +0000 (+0100)
Subject: sigh, no wrap - use direct
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c41f4ff086aa53aff1c2073376e875813d3b28e;p=soc-cocotb-sim.git

sigh, no wrap - use direct
---

diff --git a/ls180/post_pnr/cocotb/test.py b/ls180/post_pnr/cocotb/test.py
index 4a86580..810be3e 100644
--- a/ls180/post_pnr/cocotb/test.py
+++ b/ls180/post_pnr/cocotb/test.py
@@ -148,7 +148,7 @@ def wishbone_basic(dut):
 
     info = "Running Wishbone basic test"
     yield from setup_sim(dut, clk_period=clk_period, run=True)
-    master = yield from setup_jtag(wrap, tck_period = tck_period)
+    master = yield from setup_jtag(dut, tck_period = tck_period)
 
     # Load the memory address
     yield master.load_ir(cmd_MEMADDRESS)