From: Nanley Chery <nanley.g.chery@intel.com>
Date: Tue, 7 Mar 2017 19:17:05 +0000 (-0800)
Subject: intel: Correct the BDW surface state size
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c50f9903f58ef04ff393505a383d06f499f1fdc;p=mesa.git

intel: Correct the BDW surface state size

The PRMs state that this packet is 16 DWORDS long. Ensure that the last
three DWORDS are zeroed as required by the hardware when allocating a
null surface state.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
---

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 6eb1e93efd9..b4bdf2059ac 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -56,7 +56,7 @@ static const struct {
    [5] = {24, 32,  4},
    [6] = {24, 32,  4},
    [7] = {32, 32,  4, 24},
-   [8] = {52, 64, 32, 40},
+   [8] = {64, 64, 32, 40},
    [9] = {64, 64, 32, 40},
 };
 
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 501531d4ad4..f8682932172 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -46,10 +46,9 @@ static uint32_t *
 gen8_allocate_surface_state(struct brw_context *brw,
                             uint32_t *out_offset, int index)
 {
-   int dwords = brw->gen >= 9 ? 16 : 13;
    uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-                                      dwords * 4, 64, index, out_offset);
-   memset(surf, 0, dwords * 4);
+                                      64, 64, index, out_offset);
+   memset(surf, 0, 64);
    return surf;
 }