From: Paul Mackerras Date: Wed, 5 Jul 2023 09:25:28 +0000 (+1000) Subject: tests: Add a test for prefixed instructions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c5a2bcaf4dc72bed27099a7270e4e4991815ca9;p=microwatt.git tests: Add a test for prefixed instructions Signed-off-by: Paul Mackerras --- diff --git a/tests/prefix/Makefile b/tests/prefix/Makefile new file mode 100644 index 0000000..038ec2a --- /dev/null +++ b/tests/prefix/Makefile @@ -0,0 +1,3 @@ +TEST=prefix + +include ../Makefile.test diff --git a/tests/prefix/head.S b/tests/prefix/head.S new file mode 100644 index 0000000..961c2a9 --- /dev/null +++ b/tests/prefix/head.S @@ -0,0 +1,247 @@ +/* Copyright 2013-2014 IBM Corp. + * Copyright 2023 Paul Mackerras . + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* Load an immediate 64-bit value into a register */ +#define LOAD_IMM64(r, e) \ + lis r,(e)@highest; \ + ori r,r,(e)@higher; \ + rldicr r,r, 32, 31; \ + oris r,r, (e)@h; \ + ori r,r, (e)@l; + + .section ".head","ax" + + /* + * Microwatt currently enters in LE mode at 0x0, so we don't need to + * do any endian fix ups + */ + . = 0 +.global _start +_start: + LOAD_IMM64(%r10,__bss_start) + LOAD_IMM64(%r11,__bss_end) + subf %r11,%r10,%r11 + addi %r11,%r11,63 + srdi. %r11,%r11,6 + beq 2f + mtctr %r11 +1: dcbz 0,%r10 + addi %r10,%r10,64 + bdnz 1b + +2: LOAD_IMM64(%r1,__stack_top) + li %r0,0 + stdu %r0,-16(%r1) + LOAD_IMM64(%r10, die) + mtsprg0 %r10 + LOAD_IMM64(%r12, main) + mtctr %r12 + bctrl +die: attn // terminate on exit + b . + +.global trapit +trapit: + mflr %r0 + std %r0,16(%r1) + stdu %r1,-256(%r1) + mtsprg1 %r1 + r = 14 + .rept 18 + std r,r*8(%r1) + r = r + 1 + .endr + mfcr %r0 + stw %r0,13*8(%r1) + LOAD_IMM64(%r10, ret) + mtsprg0 %r10 + mr %r12,%r4 + mtctr %r4 + bctrl +ret: + mfsprg1 %r1 + LOAD_IMM64(%r10, die) + mtsprg0 %r10 + r = 14 + .rept 18 + ld r,r*8(%r1) + r = r + 1 + .endr + lwz %r0,13*8(%r1) + mtcr %r0 + ld %r0,256+16(%r1) + addi %r1,%r1,256 + mtlr %r0 + blr + +#define EXCEPTION(nr) \ + .= nr ;\ + mfsprg0 %r0 ;\ + mtctr %r0 ;\ + li %r3,nr ;\ + bctr + + EXCEPTION(0x300) + EXCEPTION(0x380) + EXCEPTION(0x400) + EXCEPTION(0x480) + EXCEPTION(0x500) + EXCEPTION(0x600) + EXCEPTION(0x700) + EXCEPTION(0x800) + EXCEPTION(0x900) + EXCEPTION(0x980) + EXCEPTION(0xa00) + EXCEPTION(0xb00) + EXCEPTION(0xc00) + EXCEPTION(0xd00) + EXCEPTION(0xe00) + EXCEPTION(0xe20) + EXCEPTION(0xe40) + EXCEPTION(0xe60) + EXCEPTION(0xe80) + EXCEPTION(0xf00) + EXCEPTION(0xf20) + EXCEPTION(0xf40) + EXCEPTION(0xf60) + EXCEPTION(0xf80) + + . = 0x1000 + .globl test_paddi +test_paddi: + nop + nop + .machine "power10" + paddi %r3,%r3,0x123456789,0 + blr + + .globl test_paddi_r +test_paddi_r: + nop + nop + paddi %r3,0,0x123456789 - 0x101c,1 + blr + + .globl test_paddi_neg +test_paddi_neg: + nop + nop + paddi %r3,%r3,-0x123456789,0 + blr + + .globl test_pld +test_pld: + nop + nop + pld %r4,lvar(0) + std %r4,0(%r3) + li %r3,0 + blr + + .globl test_plfd +test_plfd: + nop + nop + plfd %f0,fpvar(0) + stfd %f0,0(%r3) + blr + + . = 0x1074 + .globl test_paddi_mis +test_paddi_mis: + nop + nop + .long 0x06012345 + .long 0x38636789 + blr + + .globl test_pstd +test_pstd: + nop + nop + pstd %r3,lvar(0) + li %r3,0 + blr + + .globl test_plbz +test_plbz: + nop + nop + plbz %r4,bvar(0) + std %r4,0(%r3) + li %r3,0 + blr + + .globl test_pstb +test_pstb: + nop + nop + pstb %r3,bvar(0) + li %r3,0 + blr + + .globl test_plha +test_plha: + nop + nop + plha %r4,hvar(0) + std %r4,0(%r3) + li %r3,0 + blr + + .globl test_plhz +test_plhz: + nop + nop + plhz %r4,hvar(0) + std %r4,0(%r3) + li %r3,0 + blr + + .globl test_psth +test_psth: + nop + nop + psth %r3,hvar(0) + li %r3,0 + blr + + .globl test_plwa +test_plwa: + nop + nop + plwa %r4,wvar(0) + std %r4,0(%r3) + li %r3,0 + blr + + .globl test_plwz +test_plwz: + nop + nop + plwz %r4,wvar(0) + std %r4,0(%r3) + li %r3,0 + blr + + .globl test_pstw +test_pstw: + nop + nop + pstw %r3,wvar(0) + li %r3,0 + blr diff --git a/tests/prefix/powerpc.lds b/tests/prefix/powerpc.lds new file mode 100644 index 0000000..99611ab --- /dev/null +++ b/tests/prefix/powerpc.lds @@ -0,0 +1,27 @@ +SECTIONS +{ + . = 0; + _start = .; + .head : { + KEEP(*(.head)) + } + . = ALIGN(0x1000); + .text : { *(.text) *(.text.*) *(.rodata) *(.rodata.*) } + . = ALIGN(0x1000); + .data : { *(.data) *(.data.*) *(.got) *(.toc) } + . = ALIGN(0x80); + __bss_start = .; + .bss : { + *(.dynsbss) + *(.sbss) + *(.scommon) + *(.dynbss) + *(.bss) + *(.common) + *(.bss.*) + } + . = ALIGN(0x80); + __bss_end = .; + . = . + 0x4000; + __stack_top = .; +} diff --git a/tests/prefix/prefix.c b/tests/prefix/prefix.c new file mode 100644 index 0000000..94ac500 --- /dev/null +++ b/tests/prefix/prefix.c @@ -0,0 +1,214 @@ +#include +#include +#include + +#include "console.h" + +#define MSR_LE 0x1 +#define MSR_DR 0x10 +#define MSR_IR 0x20 +#define MSR_SF 0x8000000000000000ul + +#define DSISR 18 +#define DAR 19 +#define SRR0 26 +#define SRR1 27 +#define PID 48 +#define PTCR 464 + +extern long trapit(long arg, long (*func)(long)); +extern long test_paddi(long arg); +extern long test_paddi_r(long arg); +extern long test_paddi_neg(long arg); +extern long test_paddi_mis(long arg); +extern long test_plbz(long arg); +extern long test_pld(long arg); +extern long test_plha(long arg); +extern long test_plhz(long arg); +extern long test_plwa(long arg); +extern long test_plwz(long arg); +extern long test_pstb(long arg); +extern long test_pstd(long arg); +extern long test_psth(long arg); +extern long test_pstw(long arg); +extern long test_plfd(long arg); + +static inline unsigned long mfspr(int sprnum) +{ + long val; + + __asm__ volatile("mfspr %0,%1" : "=r" (val) : "i" (sprnum)); + return val; +} + +static inline void mtspr(int sprnum, unsigned long val) +{ + __asm__ volatile("mtspr %0,%1" : : "i" (sprnum), "r" (val)); +} + +void print_string(const char *str) +{ + for (; *str; ++str) + putchar(*str); +} + +void print_hex(unsigned long val, int ndigits, const char *str) +{ + int i, x; + + for (i = (ndigits - 1) * 4; i >= 0; i -= 4) { + x = (val >> i) & 0xf; + if (x >= 10) + putchar(x + 'a' - 10); + else + putchar(x + '0'); + } + print_string(str); +} + +// i < 100 +void print_test_number(int i) +{ + print_string("test "); + putchar(48 + i/10); + putchar(48 + i%10); + putchar(':'); +} + +long int prefix_test_1(void) +{ + long int ret; + + ret = trapit(0x321, test_paddi); + if (ret != 0x123456789 + 0x321) + return ret; + ret = trapit(0x322, test_paddi_r); + if (ret != 0x123456789) + return ret; + ret = trapit(0x323, test_paddi_neg); + if (ret != 0x323 - 0x123456789) + return ret; + return 0; +} + +double fpvar = 123.456; + +long int prefix_test_2(void) +{ + long int ret; + double x; + + ret = trapit(0x123, test_paddi_mis); + if (ret != 0x600) + return 1; + if (mfspr(SRR0) != (unsigned long)&test_paddi_mis + 8) + return 2; + if (mfspr(SRR1) != (MSR_SF | MSR_LE | (1ul << (63 - 35)) | (1ul << (63 - 34)))) + return 3; + + ret = trapit((long)&x, test_plfd); + if (ret != 0x800) + return ret; + if (mfspr(SRR0) != (unsigned long)&test_plfd + 8) + return 6; + if (mfspr(SRR1) != (MSR_SF | MSR_LE | (1ul << (63 - 34)))) + return 7; + return 0; +} + +unsigned char bvar = 0x63; +long lvar = 0xfedcba987654; +unsigned short hvar = 0xffee; +unsigned int wvar = 0x80457788; + +long int prefix_test_3(void) +{ + long int ret; + long int x; + + ret = trapit((long)&x, test_pld); + if (ret) + return ret | 1; + if (x != lvar) + return 2; + ret = trapit(1234, test_pstd); + if (ret) + return ret | 2; + if (lvar != 1234) + return 3; + + ret = trapit((long)&x, test_plbz); + if (ret) + return ret | 0x10; + if (x != bvar) + return 0x11; + ret = trapit(0xaa, test_pstb); + if (ret) + return ret | 0x12; + if (bvar != 0xaa) + return 0x13; + + ret = trapit((long)&x, test_plhz); + if (ret) + return ret | 0x20; + if (x != hvar) + return 0x21; + ret = trapit((long)&x, test_plha); + if (ret) + return ret | 0x22; + if (x != (signed short)hvar) + return 0x23; + ret = trapit(0x23aa, test_psth); + if (ret) + return ret | 0x24; + if (hvar != 0x23aa) + return 0x25; + + ret = trapit((long)&x, test_plwz); + if (ret) + return ret | 0x30; + if (x != wvar) + return 0x31; + ret = trapit((long)&x, test_plwa); + if (ret) + return ret | 0x32; + if (x != (signed int)wvar) + return 0x33; + ret = trapit(0x23aaf44f, test_pstw); + if (ret) + return ret | 0x34; + if (wvar != 0x23aaf44f) + return 0x35; + return 0; +} + +int fail = 0; + +void do_test(int num, long int (*test)(void)) +{ + long int ret; + + print_test_number(num); + ret = test(); + if (ret == 0) { + print_string("PASS\r\n"); + } else { + fail = 1; + print_string("FAIL "); + print_hex(ret, 16, " SRR0="); + print_hex(mfspr(SRR0), 16, " SRR1="); + print_hex(mfspr(SRR1), 16, "\r\n"); + } +} + +int main(void) +{ + console_init(); + //init_mmu(); + + do_test(1, prefix_test_1); + do_test(2, prefix_test_2); + do_test(3, prefix_test_3); + + return fail; +} diff --git a/tests/test_prefix.bin b/tests/test_prefix.bin new file mode 100755 index 0000000..a5f9ff7 Binary files /dev/null and b/tests/test_prefix.bin differ diff --git a/tests/test_prefix.console_out b/tests/test_prefix.console_out new file mode 100644 index 0000000..623335d --- /dev/null +++ b/tests/test_prefix.console_out @@ -0,0 +1,3 @@ +test 01:PASS +test 02:PASS +test 03:PASS diff --git a/tests/test_prefix.metavalue b/tests/test_prefix.metavalue new file mode 100644 index 0000000..64bb6b7 --- /dev/null +++ b/tests/test_prefix.metavalue @@ -0,0 +1 @@ +30