From: eddiehung Date: Sun, 3 May 2015 11:53:09 +0000 (+0100) Subject: Fix for all zero mask X-Git-Tag: yosys-0.7~186^2~3^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c623182393aa2e8445336a99f0cfd4bc7c7e88f;p=yosys.git Fix for all zero mask --- diff --git a/Makefile b/Makefile index f1188da2e..d41bec187 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ -CONFIG := clang +CONFIG := icc # CONFIG := gcc # CONFIG := gcc-4.6 # CONFIG := emcc @@ -109,6 +109,10 @@ ABCMKARGS += ARCHFLAGS="-DSIZEOF_VOID_P=4 -DSIZEOF_LONG=4 -DSIZEOF_INT=4 -DWIN32 ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" READLINE=0 CC="$(CXX)" CXX="$(CXX)" EXE = .exe +else ifeq ($(CONFIG),icc) +CXX = icpc +CXXFLAGS += -std=gnu++0x -Os + else ifneq ($(CONFIG),none) $(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.6, emcc, none) endif diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 3a4618a90..2734ca321 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -234,13 +234,24 @@ struct BlifDumper f << stringf(" %s", cstr(output)); f << stringf("\n"); RTLIL::SigSpec mask = cell->parameters.at("\\LUT"); + bool one = false; for (int i = 0; i < (1 << width); i++) if (mask[i] == RTLIL::S1) { for (int j = width-1; j >= 0; j--) { f << ((i>>j)&1 ? '1' : '0'); } f << " 1\n"; + one = true; } + /* For some reason, sometimes we get LUTs with + * an all zero mask, which won't give any + * .names entries, so write one entry with + * all don't cares */ + if (!one) { + for (int j = width-1; j >= 0; j--) + f << '-'; + f << " 0\n"; + } continue; }