From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 9 Jan 2019 09:28:24 +0000 (+0100)
Subject: soc/cores/cpu/vexriscv: set default variant to None in add_sources
X-Git-Tag: 24jan2021_ls180~1413
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c67bac723c0f7ae6a2820358c933bcfa2cfa5a5;p=litex.git

soc/cores/cpu/vexriscv: set default variant to None in add_sources
---

diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index b79a7fd6..e7b18bf6 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -66,7 +66,7 @@ class LM32(Module):
         self.add_sources(platform, variant)
 
     @staticmethod
-    def add_sources(platform, variant):
+    def add_sources(platform, variant=None):
         vdir = os.path.join(
             os.path.abspath(os.path.dirname(__file__)), "verilog")
         platform.add_sources(os.path.join(vdir, "submodule", "rtl"),