From: Pat Haugen Date: Tue, 28 Jun 2016 03:14:54 +0000 (+0000) Subject: rs6000.md ('type' attribute): Add veclogical,veccmpfx,vecexts,vecmove insn types. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c788ce223bef845356773178b64de69e753c1b8;p=gcc.git rs6000.md ('type' attribute): Add veclogical,veccmpfx,vecexts,vecmove insn types. * config/rs6000/rs6000.md ('type' attribute): Add veclogical,veccmpfx,vecexts,vecmove insn types. (*abs2_fpr, *nabs2_fpr, *neg2_fpr, *extendsfdf2_fpr, copysign3_fcpsgn, truncdf2_internal1, neg2_internal, p8_fmrgow_, pack): Change type to fpsimple. (*xxsel, copysign3_hard, neg2_hw, abs2_hw, *nabs2_hw): Change type to vecmove. (*and3_internal, *bool3_internal, *boolc3_internal, *boolcc3_internal, *eqv3_internal, *one_cmpl3_internal, *ieee_128bit_vsx_neg2_internal, *ieee_128bit_vsx_abs2_internal, *ieee_128bit_vsx_nabs2_internal, extendkftf2, trunctfkf2, *ieee128_mfvsrd_64bit, *ieee128_mfvsrd_32bit, *ieee128_mtvsrd_64bit, *ieee128_mtvsrd_32bit): Change type to veclogical. (mov_hardfloat, *mov_hardfloat32, *mov_hardfloat64, *movdi_internal32, *movdi_internal64): Update insn types. * config/rs6000/vsx.md (*vsx_le_undo_permute_, vsx_extract_): Change type to veclogical. (*vsx_xxsel, *vsx_xxsel_uns): Change type to vecmove. (vsx_sign_extend_qi_, *vsx_sign_extend_hi_, *vsx_sign_extend_si_v2di): Change type to vecexts. * config/rs6000/altivec.md (*altivec_mov, *altivec_movti): Change type to veclogical. (*altivec_eq, *altivec_gt, *altivec_gtu, *altivec_vcmpequ_p, *altivec_vcmpgts_p, *altivec_vcmpgtu_p): Change type to veccmpfx. (*altivec_vsel, *altivec_vsel_uns): Change type to vecmove. * config/rs6000/dfp.md (*negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr, negtd2, *abstd2_fpr, *nabstd2_fpr): Change type to fpsimple. * config/rs6000/40x.md (ppc405-float): Add fpsimple. * config/rs6000/440.md (ppc440-fp): Add fpsimple. * config/rs6000/476.md (ppc476-fp): Add fpsimple. * config/rs6000/601.md (ppc601-fp): Add fpsimple. * config/rs6000/603.md (ppc603-fp): Add fpsimple. * config/rs6000/6xx.md (ppc604-fp): Add fpsimple. * config/rs6000/7xx.md (ppc750-fp): Add fpsimple. (ppc7400-vecsimple): Add veclogical, vecmove, veccmpfx. * config/rs6000/7450.md (ppc7450-fp): Add fpsimple. (ppc7450-vecsimple): Add veclogical, vecmove. (ppc7450-veccmp): Add veccmpfx. * config/rs6000/8540.md (ppc8540_simple_vector): Add veclogical, vecmove. (ppc8540_vector_compare): Add veccmpfx. * config/rs6000/a2.md (ppca2-fp): Add fpsimple. * config/rs6000/cell.md (cell-fp): Add fpsimple. (cell-vecsimple): Add veclogical, vecmove. (cell-veccmp): Add veccmpfx. * config/rs6000/e300c2c3.md (ppce300c3_fp): Add fpsimple. * config/rs6000/e6500.md (e6500_vecsimple): Add veclogical, vecmove, veccmpfx. * config/rs6000/mpc.md (mpccore-fp): Add fpsimple. * config/rs6000/power4.md (power4-fp): Add fpsimple. (power4-vecsimple): Add veclogical, vecmove. (power4-veccmp): Add veccmpfx. * config/rs6000/power5.md (power5-fp): Add fpsimple. * config/rs6000/power6.md (power6-fp): Add fpsimple. (power6-vecsimple): Add veclogical, vecmove. (power6-veccmp): Add veccmpfx. * config/rs6000/power7.md (power7-fp): Add fpsimple. (power7-vecsimple): Add veclogical, vecmove, veccmpfx. * config/rs6000/power8.md (power8-fp): Add fpsimple. (power8-vecsimple): Add veclogical, vecmove, veccmpfx. * config/rs6000/rs64.md (rs64a-fp): Add fpsimple. * config/rs6000/titan.md (titan_fp): Add fpsimple. * config/rs6000/xfpu.md (fp-default, fp-addsub-s, fp-addsub-d): Add fpsimple. * config/rs6000/rs6000.c (rs6000_adjust_cost): Add TYPE_FPSIMPLE. From-SVN: r237812 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0e0900fdcc5..4c91c5f8522 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,73 @@ +2016-06-27 Pat Haugen + + * config/rs6000/rs6000.md ('type' attribute): Add + veclogical,veccmpfx,vecexts,vecmove insn types. + (*abs2_fpr, *nabs2_fpr, *neg2_fpr, *extendsfdf2_fpr, + copysign3_fcpsgn, truncdf2_internal1, neg2_internal, + p8_fmrgow_, pack): Change type to fpsimple. + (*xxsel, copysign3_hard, neg2_hw, abs2_hw, + *nabs2_hw): Change type to vecmove. + (*and3_internal, *bool3_internal, *boolc3_internal, + *boolcc3_internal, *eqv3_internal, + *one_cmpl3_internal, *ieee_128bit_vsx_neg2_internal, + *ieee_128bit_vsx_abs2_internal, + *ieee_128bit_vsx_nabs2_internal, extendkftf2, trunctfkf2, + *ieee128_mfvsrd_64bit, *ieee128_mfvsrd_32bit, *ieee128_mtvsrd_64bit, + *ieee128_mtvsrd_32bit): Change type to veclogical. + (mov_hardfloat, *mov_hardfloat32, *mov_hardfloat64, + *movdi_internal32, *movdi_internal64): Update insn types. + * config/rs6000/vsx.md (*vsx_le_undo_permute_, + vsx_extract_): Change type to veclogical. + (*vsx_xxsel, *vsx_xxsel_uns): Change type to vecmove. + (vsx_sign_extend_qi_, *vsx_sign_extend_hi_, + *vsx_sign_extend_si_v2di): Change type to vecexts. + * config/rs6000/altivec.md (*altivec_mov, *altivec_movti): Change + type to veclogical. + (*altivec_eq, *altivec_gt, *altivec_gtu, + *altivec_vcmpequ_p, *altivec_vcmpgts_p, + *altivec_vcmpgtu_p): Change type to veccmpfx. + (*altivec_vsel, *altivec_vsel_uns): Change type to vecmove. + * config/rs6000/dfp.md (*negdd2_fpr, *absdd2_fpr, *nabsdd2_fpr, + negtd2, *abstd2_fpr, *nabstd2_fpr): Change type to fpsimple. + * config/rs6000/40x.md (ppc405-float): Add fpsimple. + * config/rs6000/440.md (ppc440-fp): Add fpsimple. + * config/rs6000/476.md (ppc476-fp): Add fpsimple. + * config/rs6000/601.md (ppc601-fp): Add fpsimple. + * config/rs6000/603.md (ppc603-fp): Add fpsimple. + * config/rs6000/6xx.md (ppc604-fp): Add fpsimple. + * config/rs6000/7xx.md (ppc750-fp): Add fpsimple. + (ppc7400-vecsimple): Add veclogical, vecmove, veccmpfx. + * config/rs6000/7450.md (ppc7450-fp): Add fpsimple. + (ppc7450-vecsimple): Add veclogical, vecmove. + (ppc7450-veccmp): Add veccmpfx. + * config/rs6000/8540.md (ppc8540_simple_vector): Add veclogical, + vecmove. + (ppc8540_vector_compare): Add veccmpfx. + * config/rs6000/a2.md (ppca2-fp): Add fpsimple. + * config/rs6000/cell.md (cell-fp): Add fpsimple. + (cell-vecsimple): Add veclogical, vecmove. + (cell-veccmp): Add veccmpfx. + * config/rs6000/e300c2c3.md (ppce300c3_fp): Add fpsimple. + * config/rs6000/e6500.md (e6500_vecsimple): Add veclogical, vecmove, + veccmpfx. + * config/rs6000/mpc.md (mpccore-fp): Add fpsimple. + * config/rs6000/power4.md (power4-fp): Add fpsimple. + (power4-vecsimple): Add veclogical, vecmove. + (power4-veccmp): Add veccmpfx. + * config/rs6000/power5.md (power5-fp): Add fpsimple. + * config/rs6000/power6.md (power6-fp): Add fpsimple. + (power6-vecsimple): Add veclogical, vecmove. + (power6-veccmp): Add veccmpfx. + * config/rs6000/power7.md (power7-fp): Add fpsimple. + (power7-vecsimple): Add veclogical, vecmove, veccmpfx. + * config/rs6000/power8.md (power8-fp): Add fpsimple. + (power8-vecsimple): Add veclogical, vecmove, veccmpfx. + * config/rs6000/rs64.md (rs64a-fp): Add fpsimple. + * config/rs6000/titan.md (titan_fp): Add fpsimple. + * config/rs6000/xfpu.md (fp-default, fp-addsub-s, fp-addsub-d): Add + fpsimple. + * config/rs6000/rs6000.c (rs6000_adjust_cost): Add TYPE_FPSIMPLE. + 2016-06-27 Peter Bergner PR target/71656 diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md index 91e5cffaa32..98d9ae02ba4 100644 --- a/gcc/config/rs6000/40x.md +++ b/gcc/config/rs6000/40x.md @@ -119,6 +119,6 @@ "bpu_40x") (define_insn_reservation "ppc405-float" 11 - (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,dmul,sdiv,ddiv") + (and (eq_attr "type" "fpload,fpstore,fpcompare,fp,fpsimple,dmul,sdiv,ddiv") (eq_attr "cpu" "ppc405")) "fpu_405*10") diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md index 6d07ef3ea3c..c33f4accb00 100644 --- a/gcc/config/rs6000/440.md +++ b/gcc/config/rs6000/440.md @@ -107,7 +107,7 @@ "ppc440_issue,ppc440_f_pipe+ppc440_i_pipe") (define_insn_reservation "ppc440-fp" 5 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "ppc440")) "ppc440_issue,ppc440_f_pipe") diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md index 8c266b992da..4cae8fcc9e0 100644 --- a/gcc/config/rs6000/476.md +++ b/gcc/config/rs6000/476.md @@ -124,7 +124,7 @@ ppc476_f_pipe+ppc476_i_pipe") (define_insn_reservation "ppc476-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "ppc476")) "ppc476_issue_fp,\ ppc476_f_pipe") diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md index e34c9bf20f1..aa869d86d8a 100644 --- a/gcc/config/rs6000/601.md +++ b/gcc/config/rs6000/601.md @@ -86,7 +86,7 @@ "(fpu_ppc601+iu_ppc601*2),nothing*2,bpu_ppc601") (define_insn_reservation "ppc601-fp" 4 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppc601")) "fpu_ppc601") diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md index 3b07461bf0e..052c1c1c95a 100644 --- a/gcc/config/rs6000/603.md +++ b/gcc/config/rs6000/603.md @@ -105,7 +105,7 @@ "(fpu_603+iu_603*2),bpu_603") (define_insn_reservation "ppc603-fp" 3 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppc603")) "fpu_603") diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md index 29893aeeefd..3ab80a2b263 100644 --- a/gcc/config/rs6000/6xx.md +++ b/gcc/config/rs6000/6xx.md @@ -160,7 +160,7 @@ "fpu_6xx") (define_insn_reservation "ppc604-fp" 3 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppc604,ppc604e,ppc620")) "fpu_6xx") diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md index 81463693999..0ebf6fa0cd5 100644 --- a/gcc/config/rs6000/7450.md +++ b/gcc/config/rs6000/7450.md @@ -120,7 +120,7 @@ "ppc7450_du,fpu_7450") (define_insn_reservation "ppc7450-fp" 5 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "ppc7450")) "ppc7450_du,fpu_7450") @@ -162,7 +162,7 @@ ;; Altivec (define_insn_reservation "ppc7450-vecsimple" 1 - (and (eq_attr "type" "vecsimple") + (and (eq_attr "type" "vecsimple,veclogical,vecmove") (eq_attr "cpu" "ppc7450")) "ppc7450_du,ppc7450_vec_du,vecsmpl_7450") @@ -172,7 +172,7 @@ "ppc7450_du,ppc7450_vec_du,veccmplx_7450") (define_insn_reservation "ppc7450-veccmp" 2 - (and (eq_attr "type" "veccmp") + (and (eq_attr "type" "veccmp,veccmpfx") (eq_attr "cpu" "ppc7450")) "ppc7450_du,ppc7450_vec_du,veccmplx_7450") diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md index 1da48b77fd9..70e2eb17f12 100644 --- a/gcc/config/rs6000/7xx.md +++ b/gcc/config/rs6000/7xx.md @@ -113,7 +113,7 @@ "ppc750_du,fpu_7xx") (define_insn_reservation "ppc750-fp" 3 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppc750,ppc7400")) "ppc750_du,fpu_7xx") @@ -165,7 +165,7 @@ ;; Altivec (define_insn_reservation "ppc7400-vecsimple" 1 - (and (eq_attr "type" "vecsimple,veccmp") + (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx") (eq_attr "cpu" "ppc7400")) "ppc750_du,ppc7400_vec_du,veccmplx_7xx") diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md index ae4e45f89bb..f39f1f67513 100644 --- a/gcc/config/rs6000/8540.md +++ b/gcc/config/rs6000/8540.md @@ -190,7 +190,7 @@ ;; Simple vector (define_insn_reservation "ppc8540_simple_vector" 1 - (and (eq_attr "type" "vecsimple") + (and (eq_attr "type" "vecsimple,veclogical,vecmove") (eq_attr "cpu" "ppc8540,ppc8548")) "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") @@ -202,7 +202,7 @@ ;; Vector compare (define_insn_reservation "ppc8540_vector_compare" 1 - (and (eq_attr "type" "veccmp") + (and (eq_attr "type" "veccmp,veccmpfx") (eq_attr "cpu" "ppc8540,ppc8548")) "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") diff --git a/gcc/config/rs6000/a2.md b/gcc/config/rs6000/a2.md index 1fcf1cfb204..e0b800ce61b 100644 --- a/gcc/config/rs6000/a2.md +++ b/gcc/config/rs6000/a2.md @@ -81,7 +81,7 @@ ;; D.8.1 (define_insn_reservation "ppca2-fp" 6 - (and (eq_attr "type" "fp") ;; Ignore fpsimple insn types (SPE only). + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppca2")) "axu") diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 0cd67a4ec99..fcc00b515bb 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -242,7 +242,7 @@ default: gcc_unreachable (); } } - [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*,*") + [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*,*") (set_attr "length" "4,4,4,20,20,20,4,8,32")]) ;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode @@ -268,7 +268,7 @@ default: gcc_unreachable (); } } - [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")]) + [(set_attr "type" "vecstore,vecload,veclogical,store,load,*,veclogical,*")]) ;; Load up a vector with the most significant bit set by loading up -1 and ;; doing a shift left @@ -603,7 +603,7 @@ (match_operand:VI2 2 "altivec_register_operand" "v")))] "" "vcmpequ %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_gt" [(set (match_operand:VI2 0 "altivec_register_operand" "=v") @@ -611,7 +611,7 @@ (match_operand:VI2 2 "altivec_register_operand" "v")))] "" "vcmpgts %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_gtu" [(set (match_operand:VI2 0 "altivec_register_operand" "=v") @@ -619,7 +619,7 @@ (match_operand:VI2 2 "altivec_register_operand" "v")))] "" "vcmpgtu %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_eqv4sf" [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") @@ -654,7 +654,7 @@ (match_operand:VM 3 "altivec_register_operand" "v")))] "VECTOR_MEM_ALTIVEC_P (mode)" "vsel %0,%3,%2,%1" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) (define_insn "*altivec_vsel_uns" [(set (match_operand:VM 0 "altivec_register_operand" "=v") @@ -665,7 +665,7 @@ (match_operand:VM 3 "altivec_register_operand" "v")))] "VECTOR_MEM_ALTIVEC_P (mode)" "vsel %0,%3,%2,%1" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) ;; Fused multiply add. @@ -2283,7 +2283,7 @@ (match_dup 2)))] "" "vcmpequ. %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpgts_p" [(set (reg:CC 74) @@ -2295,7 +2295,7 @@ (match_dup 2)))] "" "vcmpgts. %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpgtu_p" [(set (reg:CC 74) @@ -2307,7 +2307,7 @@ (match_dup 2)))] "" "vcmpgtu. %0,%1,%2" - [(set_attr "type" "veccmp")]) + [(set_attr "type" "veccmpfx")]) (define_insn "*altivec_vcmpeqfp_p" [(set (reg:CC 74) diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md index b780f09efe0..7eee77cd5f1 100644 --- a/gcc/config/rs6000/cell.md +++ b/gcc/config/rs6000/cell.md @@ -306,7 +306,7 @@ ; Basic FP latency is 10 cycles, thoughput is 1/cycle (define_insn_reservation "cell-fp" 10 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "cell")) "slot01,vsu1_cell,vsu1_cell*8") @@ -329,7 +329,7 @@ ; VMX (define_insn_reservation "cell-vecsimple" 4 - (and (eq_attr "type" "vecsimple") + (and (eq_attr "type" "vecsimple,veclogical,vecmove") (eq_attr "cpu" "cell")) "slot01,vsu1_cell,vsu1_cell*2") @@ -341,7 +341,7 @@ ;; TODO: add support for recording instructions (define_insn_reservation "cell-veccmp" 4 - (and (eq_attr "type" "veccmp") + (and (eq_attr "type" "veccmp,veccmpfx") (eq_attr "cpu" "cell")) "slot01,vsu1_cell,vsu1_cell*2") diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index 7029eb6da38..09d0fd62081 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -89,7 +89,7 @@ (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && TARGET_FPRS" "fneg %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) (define_expand "absdd2" [(set (match_operand:DD 0 "gpc_reg_operand" "") @@ -102,14 +102,14 @@ (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] "TARGET_HARD_FLOAT && TARGET_FPRS" "fabs %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) (define_insn "*nabsdd2_fpr" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") (neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))] "TARGET_HARD_FLOAT && TARGET_FPRS" "fnabs %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) (define_expand "negtd2" [(set (match_operand:TD 0 "gpc_reg_operand" "") @@ -124,7 +124,7 @@ "@ fneg %0,%1 fneg %0,%1\;fmr %L0,%L1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "length" "4,8")]) (define_expand "abstd2" @@ -140,7 +140,7 @@ "@ fabs %0,%1 fabs %0,%1\;fmr %L0,%L1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "length" "4,8")]) (define_insn "*nabstd2_fpr" @@ -150,7 +150,7 @@ "@ fnabs %0,%1 fnabs %0,%1\;fmr %L0,%L1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "length" "4,8")]) ;; Hardware support for decimal floating point operations. diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md index 5865e95e2d2..e48979979ab 100644 --- a/gcc/config/rs6000/e300c2c3.md +++ b/gcc/config/rs6000/e300c2c3.md @@ -150,7 +150,7 @@ "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") (define_insn_reservation "ppce300c3_fp" 3 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "ppce300c3")) "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md index 428222d14bf..e094192d61d 100644 --- a/gcc/config/rs6000/e6500.md +++ b/gcc/config/rs6000/e6500.md @@ -205,7 +205,7 @@ ;; VSFX. (define_insn_reservation "e6500_vecsimple" 1 - (and (eq_attr "type" "vecsimple,veccmp") + (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx") (eq_attr "cpu" "ppce6500")) "e6500_decode,e6500_vec") diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md index 010dc9444e0..42cb11a5980 100644 --- a/gcc/config/rs6000/mpc.md +++ b/gcc/config/rs6000/mpc.md @@ -81,7 +81,7 @@ "fpu_mpc,bpu_mpc") (define_insn_reservation "mpccore-fp" 4 - (and (eq_attr "type" "fp") + (and (eq_attr "type" "fp,fpsimple") (eq_attr "cpu" "mpccore")) "fpu_mpc*2") diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md index 7b0ccbedaac..84ac439fe97 100644 --- a/gcc/config/rs6000/power4.md +++ b/gcc/config/rs6000/power4.md @@ -381,7 +381,7 @@ ; Basic FP latency is 6 cycles (define_insn_reservation "power4-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "power4")) "fpq_power4") @@ -410,7 +410,7 @@ ; VMX (define_insn_reservation "power4-vecsimple" 2 - (and (eq_attr "type" "vecsimple") + (and (eq_attr "type" "vecsimple,veclogical,vecmove") (eq_attr "cpu" "power4")) "vq_power4") @@ -421,7 +421,7 @@ ; vecfp compare (define_insn_reservation "power4-veccmp" 8 - (and (eq_attr "type" "veccmp") + (and (eq_attr "type" "veccmp,veccmpfx") (eq_attr "cpu" "power4")) "vq_power4") diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md index 2d7c15e59c0..b00d5ead143 100644 --- a/gcc/config/rs6000/power5.md +++ b/gcc/config/rs6000/power5.md @@ -322,7 +322,7 @@ ; Basic FP latency is 6 cycles (define_insn_reservation "power5-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "power5")) "fpq_power5") diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md index 15d31eb81a2..5bff2a73a7b 100644 --- a/gcc/config/rs6000/power6.md +++ b/gcc/config/rs6000/power6.md @@ -500,7 +500,7 @@ (define_bypass 9 "power6-mtcr" "power6-branch") (define_insn_reservation "power6-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "power6")) "FPU_power6") @@ -556,7 +556,7 @@ "LSF_power6") (define_insn_reservation "power6-vecsimple" 3 - (and (eq_attr "type" "vecsimple") + (and (eq_attr "type" "vecsimple,veclogical,vecmove") (eq_attr "cpu" "power6")) "FPU_power6") @@ -568,7 +568,7 @@ (define_bypass 4 "power6-vecsimple" "power6-vecstore" ) (define_insn_reservation "power6-veccmp" 1 - (and (eq_attr "type" "veccmp") + (and (eq_attr "type" "veccmp,veccmpfx") (eq_attr "cpu" "power6")) "FPU_power6") diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md index 9c6326dd26b..adda1df84c5 100644 --- a/gcc/config/rs6000/power7.md +++ b/gcc/config/rs6000/power7.md @@ -292,7 +292,7 @@ ; VS Unit (includes FP/VSX/VMX/DFP) (define_insn_reservation "power7-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "power7")) "DU_power7,VSU_power7") @@ -324,7 +324,7 @@ "DU_power7,VSU_power7") (define_insn_reservation "power7-vecsimple" 2 - (and (eq_attr "type" "vecsimple,veccmp") + (and (eq_attr "type" "vecsimple,veclogical,vecmove,veccmp,veccmpfx") (eq_attr "cpu" "power7")) "DU_power7,vsu1_power7") diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md index 6b6f0ffb8de..c0c06c5cbe9 100644 --- a/gcc/config/rs6000/power8.md +++ b/gcc/config/rs6000/power8.md @@ -317,7 +317,7 @@ ; VS Unit (includes FP/VSX/VMX/DFP/Crypto) (define_insn_reservation "power8-fp" 6 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "power8")) "DU_any_power8,VSU_power8") @@ -350,7 +350,8 @@ "DU_any_power8,VSU_power8") (define_insn_reservation "power8-vecsimple" 2 - (and (eq_attr "type" "vecperm,vecsimple,veccmp") + (and (eq_attr "type" "vecperm,vecsimple,veclogical,vecmove,veccmp, + veccmpfx") (eq_attr "cpu" "power8")) "DU_any_power8,VSU_power8") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f81ce613637..12b2e4d37fc 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -30171,7 +30171,9 @@ rs6000_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost) switch (attr_type) { case TYPE_FP: - if (get_attr_type (dep_insn) == TYPE_FP) + case TYPE_FPSIMPLE: + if (get_attr_type (dep_insn) == TYPE_FP + || get_attr_type (dep_insn) == TYPE_FPSIMPLE) return 1; break; case TYPE_FPLOAD: diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9a3907993ba..bb31e41e256 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -183,6 +183,7 @@ brinc, vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm, vecfloat,vecfdiv,vecdouble,mffgpr,mftgpr,crypto, + veclogical,veccmpfx,vecexts,vecmove, htm" (const_string "integer")) @@ -4354,7 +4355,7 @@ "@ fabs %0,%1 xsabsdp %x0,%x1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "fp_type" "fp_addsub_")]) (define_insn "*nabs2_fpr" @@ -4366,7 +4367,7 @@ "@ fnabs %0,%1 xsnabsdp %x0,%x1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "fp_type" "fp_addsub_")]) (define_expand "neg2" @@ -4382,7 +4383,7 @@ "@ fneg %0,%1 xsnegdp %x0,%x1" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "fp_type" "fp_addsub_")]) (define_expand "add3" @@ -4543,7 +4544,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "fp,fp,fpload,fp,fp,fpload,fpload")]) + [(set_attr "type" "fp,fpsimple,fpload,fp,fpsimple,fpload,fpload")]) (define_expand "truncdfsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "") @@ -4633,7 +4634,7 @@ "@ fcpsgn %0,%2,%1 xscpsgndp %x0,%x2,%x1" - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a ;; fsel instruction and some auxiliary computations. Then we just have a @@ -4846,7 +4847,7 @@ (match_operand:SFDF 4 "vsx_register_operand" "")))] "TARGET_P9_MINMAX" "xxsel %x0,%x1,%x3,%x4" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) ;; Conversions to and from floating-point. @@ -6092,7 +6093,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6128,7 +6129,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6166,7 +6167,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6226,7 +6227,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6284,7 +6285,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6340,7 +6341,7 @@ [(set (attr "type") (if_then_else (match_test "vsx_register_operand (operands[0], mode)") - (const_string "vecsimple") + (const_string "veclogical") (const_string "integer"))) (set (attr "length") (if_then_else @@ -6655,7 +6656,7 @@ mt%0 %1 mf%1 %0 nop" - [(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*") + [(set_attr "type" "*,load,store,fpsimple,fpsimple,veclogical,integer,fpload,fpload,fpstore,fpstore,fpload,fpstore,mffgpr,mftgpr,mtjmpr,mfjmpr,*") (set_attr "length" "4")]) (define_insn "*mov_softfloat" @@ -6790,7 +6791,7 @@ # # #" - [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,two,store,load,two") + [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two") (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")]) (define_insn "*mov_softfloat32" @@ -6835,7 +6836,7 @@ mffgpr %0,%1 mfvsrd %0,%x1 mtvsrd %x0,%1" - [(set_attr "type" "fpstore,fpload,fp,fpload,fpstore,fpload,fpstore,vecsimple,vecsimple,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr") + [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr") (set_attr "length" "4")]) (define_insn "*mov_softfloat64" @@ -7046,7 +7047,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "fp")]) + [(set_attr "type" "fpsimple")]) (define_insn "truncdf2_internal2" [(set (match_operand:DF 0 "gpc_reg_operand" "=d") @@ -7279,7 +7280,7 @@ else return \"fneg %0,%1\;fneg %L0,%L1\"; }" - [(set_attr "type" "fp") + [(set_attr "type" "fpsimple") (set_attr "length" "8")]) (define_expand "abs2" @@ -7414,7 +7415,7 @@ (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlxor %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "veclogical")]) ;; IEEE 128-bit absolute value (define_insn_and_split "ieee_128bit_vsx_abs2" @@ -7443,7 +7444,7 @@ (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlandc %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "veclogical")]) ;; IEEE 128-bit negative absolute value (define_insn_and_split "*ieee_128bit_vsx_nabs2" @@ -7476,7 +7477,7 @@ (use (match_operand:V16QI 2 "register_operand" "v"))] "TARGET_FLOAT128 && !TARGET_FLOAT128_HW" "xxlor %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "veclogical")]) ;; Float128 conversion functions. These expand to library function calls. ;; We use expand to convert from IBM double double to IEEE 128-bit @@ -7632,7 +7633,7 @@ UNSPEC_P8V_FMRGOW))] "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" "fmrgow %0,%1,%2" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "fpsimple")]) (define_insn "p8_mtvsrwz" [(set (match_operand:DF 0 "register_operand" "=d") @@ -7884,9 +7885,9 @@ # #" [(set_attr "type" - "store, load, *, fpstore, fpload, fp, - *, fpstore, fpstore, fpload, fpload, vecsimple, - vecsimple, vecsimple, vecsimple, vecsimple, vecsimple, vecsimple, + "store, load, *, fpstore, fpload, fpsimple, + *, fpstore, fpstore, fpload, fpload, veclogical, + vecsimple, vecsimple, vecsimple, veclogical, veclogical, vecsimple, vecsimple")]) (define_split @@ -7970,11 +7971,11 @@ mfvsrd %0,%x1 mtvsrd %x0,%1" [(set_attr "type" - "store, load, *, *, *, *, - fpstore, fpload, fp, fpstore, fpstore, fpload, - fpload, vecsimple, vecsimple, vecsimple, vecsimple, vecsimple, - vecsimple, vecsimple, vecsimple, mfjmpr, mtjmpr, *, - mftgpr, mffgpr, mftgpr, mffgpr") + "store, load, *, *, *, *, + fpstore, fpload, fpsimple, fpstore, fpstore, fpload, + fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical, + veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *, + mftgpr, mffgpr, mftgpr, mffgpr") (set_attr "length" "4, 4, 4, 4, 4, 20, @@ -13391,7 +13392,7 @@ operands[3] = gen_rtx_REG (mode, dest_hi); operands[4] = gen_rtx_REG (mode, dest_lo); } - [(set_attr "type" "fp,fp") + [(set_attr "type" "fpsimple,fp") (set_attr "length" "4,8")]) (define_insn "unpack" @@ -13493,7 +13494,7 @@ UNSPEC_COPYSIGN))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xscpsgnqp %0,%2,%1" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "vecmove")]) (define_insn "copysign3_soft" [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") @@ -13513,7 +13514,7 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsnegqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecmove")]) (define_insn "abs2_hw" @@ -13522,7 +13523,7 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v")))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsabsqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecmove")]) (define_insn "*nabs2_hw" @@ -13532,7 +13533,7 @@ (match_operand:IEEE128 1 "altivec_register_operand" "v"))))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "xsnabsqp %0,%1" - [(set_attr "type" "vecfloat")]) + [(set_attr "type" "vecmove")]) ;; Initially don't worry about doing fusion (define_insn "*fma4_hw" @@ -13602,7 +13603,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "*,vecsimple") + [(set_attr "type" "*,veclogical") (set_attr "length" "0,4")]) (define_insn_and_split "trunctfkf2" @@ -13618,7 +13619,7 @@ emit_note (NOTE_INSN_DELETED); DONE; } - [(set_attr "type" "*,vecsimple") + [(set_attr "type" "*,veclogical") (set_attr "length" "0,4")]) (define_insn "truncdf2_hw" @@ -13754,7 +13755,7 @@ mfvsrd %0,%x1 stxsdx %x1,%y0 xxlor %x0,%x1,%x1" - [(set_attr "type" "mftgpr,fpstore,vecsimple")]) + [(set_attr "type" "mftgpr,fpstore,veclogical")]) (define_insn "*ieee128_mfvsrd_32bit" @@ -13765,7 +13766,7 @@ "@ stxsdx %x1,%y0 xxlor %x0,%x1,%x1" - [(set_attr "type" "fpstore,vecsimple")]) + [(set_attr "type" "fpstore,veclogical")]) (define_insn "*ieee128_mfvsrwz" [(set (match_operand:SI 0 "reg_or_indexed_operand" "=r,Z") @@ -13801,7 +13802,7 @@ mtvsrd %x0,%1 lxsdx %x0,%y1 xxlor %x0,%x1,%x1" - [(set_attr "type" "mffgpr,fpload,vecsimple")]) + [(set_attr "type" "mffgpr,fpload,veclogical")]) (define_insn "*ieee128_mtvsrd_32bit" [(set (match_operand:V2DI 0 "altivec_register_operand" "=v,v") @@ -13811,7 +13812,7 @@ "@ lxsdx %x0,%y1 xxlor %x0,%x1,%x1" - [(set_attr "type" "fpload,vecsimple")]) + [(set_attr "type" "fpload,veclogical")]) ;; IEEE 128-bit instructions with round to odd semantics (define_insn "*truncdf2_odd" diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md index b730aa82ec4..e33cb785595 100644 --- a/gcc/config/rs6000/rs64.md +++ b/gcc/config/rs6000/rs64.md @@ -111,7 +111,7 @@ "mciu_rs64,fpu_rs64,bpu_rs64") (define_insn_reservation "rs64a-fp" 4 - (and (eq_attr "type" "fp,dmul") + (and (eq_attr "type" "fp,fpsimple,dmul") (eq_attr "cpu" "rs64a")) "mciu_rs64,fpu_rs64") diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md index 74389534b45..e6658d67bd3 100644 --- a/gcc/config/rs6000/titan.md +++ b/gcc/config/rs6000/titan.md @@ -156,7 +156,7 @@ ;; Make sure the "titan_fp" rule stays last, as it's a catch all for ;; double-precision and unclassified (e.g. fsel) FP-instructions (define_insn_reservation "titan_fp" 10 - (and (eq_attr "type" "fpcompare,fp,dmul") + (and (eq_attr "type" "fpcompare,fp,fpsimple,dmul") (eq_attr "cpu" "titan")) "titan_issue,titan_fp0*2,nothing*8,titan_fpwb") diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index b53655f3bde..4fa7f6a181c 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -686,7 +686,7 @@ } } [(set_attr "length" "0,4") - (set_attr "type" "vecsimple")]) + (set_attr "type" "veclogical")]) (define_insn_and_split "*vsx_le_perm_load_" [(set (match_operand:VSX_LE_128 0 "vsx_register_operand" "=") @@ -1493,7 +1493,7 @@ (match_operand:VSX_L 3 "vsx_register_operand" ",")))] "VECTOR_MEM_VSX_P (mode)" "xxsel %x0,%x3,%x2,%x1" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) (define_insn "*vsx_xxsel_uns" [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?") @@ -1504,7 +1504,7 @@ (match_operand:VSX_L 3 "vsx_register_operand" ",")))] "VECTOR_MEM_VSX_P (mode)" "xxsel %x0,%x3,%x2,%x1" - [(set_attr "type" "vecperm")]) + [(set_attr "type" "vecmove")]) ;; Copy sign (define_insn "vsx_copysign3" @@ -2158,7 +2158,7 @@ else gcc_unreachable (); } - [(set_attr "type" "vecsimple,mftgpr,mftgpr,vecperm")]) + [(set_attr "type" "veclogical,mftgpr,mftgpr,vecperm")]) ;; Optimize extracting a single scalar element from memory if the scalar is in ;; the correct location to use a single load. @@ -2704,7 +2704,7 @@ UNSPEC_VSX_SIGN_EXTEND))] "TARGET_P9_VECTOR" "vextsb2 %0,%1" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "vecexts")]) (define_insn "vsx_sign_extend_hi_" [(set (match_operand:VSINT_84 0 "vsx_register_operand" "=v") @@ -2713,7 +2713,7 @@ UNSPEC_VSX_SIGN_EXTEND))] "TARGET_P9_VECTOR" "vextsh2 %0,%1" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "vecexts")]) (define_insn "*vsx_sign_extend_si_v2di" [(set (match_operand:V2DI 0 "vsx_register_operand" "=v") @@ -2721,7 +2721,7 @@ UNSPEC_VSX_SIGN_EXTEND))] "TARGET_P9_VECTOR" "vextsw2d %0,%1" - [(set_attr "type" "vecsimple")]) + [(set_attr "type" "vecexts")]) ;; ISA 3.0 memory operations diff --git a/gcc/config/rs6000/xfpu.md b/gcc/config/rs6000/xfpu.md index 14557eb81b7..963a1b5e751 100644 --- a/gcc/config/rs6000/xfpu.md +++ b/gcc/config/rs6000/xfpu.md @@ -55,7 +55,7 @@ (define_insn_reservation "fp-default" 2 (and (and - (eq_attr "type" "fp") + (eq_attr "type" "fp,fpsimple") (eq_attr "fp_type" "fp_default")) (eq_attr "cpu" "ppc405")) "Xfpu_issue*2") @@ -67,14 +67,14 @@ (define_insn_reservation "fp-addsub-s" 14 (and (and - (eq_attr "type" "fp") + (eq_attr "type" "fp,fpsimple") (eq_attr "fp_type" "fp_addsub_s")) (eq_attr "cpu" "ppc405")) "Xfpu_issue*2,Xfpu_addsub") (define_insn_reservation "fp-addsub-d" 18 (and (and - (eq_attr "type" "fp") + (eq_attr "type" "fp,fpsimple") (eq_attr "fp_type" "fp_addsub_d")) (eq_attr "cpu" "ppc405")) "Xfpu_issue*2,Xfpu_addsub")