From: lkcl <lkcl@web>
Date: Thu, 7 Apr 2022 16:46:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2858
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c8894ca5d1b6603891e8ac72b06403144cbb6fd;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index f386181c4..6890e7a8f 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -193,14 +193,6 @@ Brief description of fields:
   VL is truncated to *exclude* the current element, otherwise it is
   included. SVSTATE.MVL is not altered: only VL.
 * **LRu**: Link Register Update, used in conjunction with LK=1.
-  - When LRu=0,LK=1, Link Register is updated unconditionally.
-  - When LRu=1,LK=1, Link Register will
-  only be updated if the Branch Condition succeeds.
-  - When LRu=1,LK=0, Link Register will only be updated if
-  the Branch Condition fails.
-  - This avoids
-  destruction of LR during loops (particularly Vertical-First
-  ones).
 * **VSb** In VLSET Mode, after testing,
   if VSb is set, VL is truncated if the test succeeds.  If VSb is clear,
   VL is truncated if a test *fails*. Masked-out (skipped)
@@ -343,6 +335,16 @@ fashion. A SIMD-based Branch Unit, receiving and processing
 multiple CR Fields covered by multiple predicate bits, would
 do the exact same thing.*
 
+## Link Register Update
+  - When LRu=0,LK=1, Link Register is updated unconditionally.
+  - When LRu=1,LK=1, Link Register will
+  only be updated if the Branch Condition succeeds.
+  - When LRu=1,LK=0, Link Register will only be updated if
+  the Branch Condition fails.
+  - This avoids
+  destruction of LR during loops (particularly Vertical-First
+  ones).
+
 ## CTR-test
 
 Where a standard Scalar v3.0B branch unconditionally decrements
@@ -380,7 +382,7 @@ It is also critical to emphasise that in this unusual mode,
 no other side-effects occur: **only** CTR is decremented, i.e. the
 rest of the Branch operation is skipped.
 
-# VLSET Mode
+## VLSET Mode
 
 VLSET Mode truncates the Vector Length so that subsequent instructions
 operate on a reduced Vector Length. This is similar to