From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 21 Sep 2019 00:58:51 +0000 (-0700)
Subject: Hell let's add the original #1381 testcase too
X-Git-Tag: working-ls180~1050^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c8de1dd180e4d6cf708700d73f29f3b581722ce;p=yosys.git

Hell let's add the original #1381 testcase too
---

diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys
index 4773d5ce3..1eb99ec37 100644
--- a/tests/techmap/autopurge.ys
+++ b/tests/techmap/autopurge.ys
@@ -1,6 +1,6 @@
-# https://github.com/YosysHQ/yosys/issues/1391
+# https://github.com/YosysHQ/yosys/issues/1381
 read_verilog <<EOT
-module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
+module sub(input i, output o, (* techmap_autopurge *) input j);
 foobar f(i, o, j);
 endmodule
 EOT
@@ -24,7 +24,16 @@ techmap -map %techmap
 hierarchy
 check -assert
 
-read_verilog -overwrite <<EOT
+# https://github.com/YosysHQ/yosys/issues/1391
+design -reset
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
 (* blackbox *)
 module sub(input i, output o, input j);
 endmodule
@@ -33,6 +42,16 @@ endmodule
 module foobar(input i, output o, input j);
 endmodule
 
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
+read_verilog -overwrite <<EOT
 module top(input i, output o);
 wire j;
 sub s0(i, o, j);