From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 13 Feb 2020 18:30:29 +0000 (-0800)
Subject: abc9_ops: sort LUT delays to be ascending
X-Git-Tag: working-ls180~780^2~30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7c92b6852f3bcc962e72bb787ac51e3f4324a4fb;p=yosys.git

abc9_ops: sort LUT delays to be ascending
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 61a3880b7..e1ab70f11 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -617,7 +617,8 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 		}
 		if (maxlut && GetSize(specify) > maxlut)
 			continue;
-		// ABC requires ascending LUT input delays
+		// ABC requires non-decreasing LUT input delays
+		std::sort(specify.begin(), specify.end());
 		table.emplace_back(GetSize(specify), module->name, it->second.as_int(), std::move(specify));
 	}
 	// ABC requires ascending size
@@ -777,6 +778,8 @@ void prep_box(RTLIL::Design *design)
 				log_assert(GetSize(src) == GetSize(dst));
 				for (auto i = 0; i < GetSize(src); i++) {
 					auto r = table.insert(std::make_pair(src[i],dst[i]));
+					if (!r.second)
+						log_error("Module '%s' contains multiple specify cells for SRC '%s' and DST '%s'.\n", log_id(module), log_signal(src[i]), log_signal(dst[i]));
 					log_assert(r.second);
 					r.first->second = std::to_string(max);
 				}