From: Michael Meissner Date: Thu, 20 Jun 2019 17:10:51 +0000 (+0000) Subject: rs6000.md (isa attribute): Add support for for a future processor. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ca50393b3bc1c148d865cbc32e72df22ddbc564;p=gcc.git rs6000.md (isa attribute): Add support for for a future processor. 2019-06-20 Michael Meissner * config/rs6000/rs6000.md (isa attribute): Add support for for a future processor. From-SVN: r272513 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d4c32201b81..7deb9d8a7aa 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-06-20 Michael Meissner + + * config/rs6000/rs6000.md (isa attribute): Add support for + for a future processor. + 2019-06-20 H.J. Lu PR target/54855 diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index eb03e4d4c1e..b04c70551c0 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -267,7 +267,8 @@ (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v,p9kf,p9tf" (const_string "any")) +(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v,p9kf,p9tf,fut" + (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? (define_attr "enabled" "" @@ -306,6 +307,10 @@ (and (eq_attr "isa" "p9tf") (match_test "FLOAT128_VECTOR_P (TFmode)")) (const_int 1) + + (and (eq_attr "isa" "fut") + (match_test "TARGET_FUTURE")) + (const_int 1) ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor