From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 26 Feb 2019 20:18:28 +0000 (-0800)
Subject: abc9 -- multiple connections for inouts
X-Git-Tag: working-ls180~1237^2~251
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7cac3b1c8bab3ba7749f4e272544f3f5f3dfa1e2;p=yosys.git

abc9 -- multiple connections for inouts
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index de47de92e..3ec365bc0 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -898,13 +898,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 				conn.first = remap_wire;
 				conn.second = signal;
 				in_wires++;
+				module->connect(conn);
 			}
 			if (w->port_output) {
 				conn.first = signal;
 				conn.second = remap_wire;
 				out_wires++;
+				module->connect(conn);
 			}
-			module->connect(conn);
 		}
 
 		//log("ABC RESULTS:        internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);