From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 16 Jan 2015 17:13:07 +0000 (+0100)
Subject: link/cont: improve timing
X-Git-Tag: 24jan2021_ls180~2572^2~58
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7ccc5f52746ac8870eea60d2571902cb58e9608e;p=litex.git

link/cont: improve timing
---

diff --git a/lib/sata/link/cont.py b/lib/sata/link/cont.py
index 8d54ad27..ece5896c 100644
--- a/lib/sata/link/cont.py
+++ b/lib/sata/link/cont.py
@@ -14,6 +14,7 @@ class SATACONTInserter(Module):
 
 		is_data = Signal()
 		was_data = Signal()
+		was_hold = Signal()
 		change = Signal()
 		self.comb += is_data.eq(sink.charisk == 0)
 
@@ -27,11 +28,10 @@ class SATACONTInserter(Module):
 				If(~is_data,
 					last_primitive.eq(sink.data),
 				),
-				was_data.eq(is_data)
+				was_data.eq(is_data),
+				was_hold.eq(last_primitive == primitives["HOLD"])
 			)
 		]
-		was_hold = last_primitive == primitives["HOLD"]
-
 		self.comb += change.eq(
 			(sink.data != last_data) |
 			(sink.charisk != last_charisk) |