From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 21 Jun 2016 06:44:20 +0000 (+0200)
Subject: Merge pull request #181 from rubund/input_logic_allowed
X-Git-Tag: yosys-0.7~190
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7cddab0788cadc220ffa098c4ac037362ad6948e;p=yosys.git

Merge pull request #181 from rubund/input_logic_allowed

Allow defining input ports as "input logic" in SystemVerilog
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7cddab0788cadc220ffa098c4ac037362ad6948e